mrs.sv « decode « core « rtl - conspiracion - Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.

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path: root/rtl/core/decode/mrs.sv

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`include "core/decode/isa.sv"
`include "core/uarch.sv"

module core_decode_mrs
(
	input  word    insn,

	output reg_num rd,
	output logic   spsr
);

	assign rd = insn `FIELD_MRS_RD;
	assign spsr = insn `FIELD_MRS_R;

endmodule