rtl/core/cp15/cyclecnt.sv


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`include "core/uarch.sv"

module core_cp15_cyclecnt
(
	input  logic     clk,
	                 rst_n,

	input  logic     halt,

	output word      read
);

	word cyclecnt;

	assign read = cyclecnt;

	always @(posedge clk or negedge rst_n)
		if(!rst_n)
			cyclecnt <= 0;
		else if(!halt)
			cyclecnt <= cyclecnt + 1;

endmodule