path: root/ip/ip_fp_add_sim/ip_fp_add.vo

//IP Functional Simulation Model
//VERSION_BEGIN 20.1 cbx_mgl 2020:11:11:17:50:46:SJ cbx_simgen 2020:11:11:17:03:37:SJ  VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463



// Copyright (C) 2020  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions 
// and other software and tools, and any partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License 
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors.  Please
// refer to the applicable agreement for further details, at
// https://fpgasoftware.intel.com/eula.

// You may only use these simulation model output files for simulation
// purposes and expressly not for synthesis or any other purposes (in which
// event Intel disclaims all warranties of any kind).


//synopsys translate_off

//synthesis_resources = lut 135 mux21 66 oper_add 7 oper_mux 68 
`timescale 1 ps / 1 ps
module  ip_fp_add
	( 
	a,
	areset,
	b,
	clk,
	en,
	q) /* synthesis synthesis_clearbox=1 */;
	input   [15:0]  a;
	input   areset;
	input   [15:0]  b;
	input   clk;
	input   [0:0]  en;
	output   [15:0]  q;

	reg	n000i;
	reg	n000l;
	reg	n000O;
	reg	n001i;
	reg	n001l;
	reg	n001O;
	reg	n00ii;
	reg	n00il;
	reg	n00iO;
	reg	n00li;
	reg	n00ll;
	reg	n00lO;
	reg	n00Oi;
	reg	n00Ol;
	reg	n00OO;
	reg	n010i;
	reg	n010l;
	reg	n010O;
	reg	n011i;
	reg	n011l;
	reg	n011O;
	reg	n01ii;
	reg	n01il;
	reg	n01iO;
	reg	n01li;
	reg	n01ll;
	reg	n01lO;
	reg	n01Oi;
	reg	n01Ol;
	reg	n01OO;
	reg	n0i1i;
	reg	n0i1l;
	reg	n0ii;
	reg	n0il;
	reg	n0iO;
	reg	n0li;
	reg	n0ll;
	reg	n0lO;
	reg	n0Oi;
	reg	n0Ol;
	reg	n100i;
	reg	n100l;
	reg	n100O;
	reg	n101i;
	reg	n101l;
	reg	n101O;
	reg	n10ii;
	reg	n10il;
	reg	n10iO;
	reg	n10li;
	reg	n10ll;
	reg	n10lO;
	reg	n10Oi;
	reg	n10Ol;
	reg	n10OO;
	reg	n110i;
	reg	n110l;
	reg	n110O;
	reg	n111i;
	reg	n111l;
	reg	n111O;
	reg	n11ii;
	reg	n11il;
	reg	n11iO;
	reg	n11li;
	reg	n11ll;
	reg	n11lO;
	reg	n11Oi;
	reg	n11Ol;
	reg	n11OO;
	reg	n1i0i;
	reg	n1i0l;
	reg	n1i0O;
	reg	n1i1i;
	reg	n1i1l;
	reg	n1i1O;
	reg	n1iii;
	reg	n1iil;
	reg	n1iiO;
	reg	n1ili;
	reg	n1ill;
	reg	n1ilO;
	reg	n1iOi;
	reg	n1iOl;
	reg	n1iOO;
	reg	n1l0i;
	reg	n1l0l;
	reg	n1l0O;
	reg	n1l1i;
	reg	n1l1l;
	reg	n1l1O;
	reg	n1lii;
	reg	n1lil;
	reg	n1liO;
	reg	n1lli;
	reg	n1lll;
	reg	n1llO;
	reg	n1lOi;
	reg	n1lOl;
	reg	n1lOO;
	reg	n1O0i;
	reg	n1O0l;
	reg	n1O0O;
	reg	n1O1i;
	reg	n1O1l;
	reg	n1O1O;
	reg	n1Oii;
	reg	n1Oil;
	reg	n1OiO;
	reg	n1Oli;
	reg	n1Oll;
	reg	n1OlO;
	reg	n1OOi;
	reg	n1OOl;
	reg	n1OOO;
	reg	ni1i;
	reg	niiii;
	reg	niilO;
	reg	nl0OO;
	reg	nli0i;
	reg	nli0l;
	reg	nli0O;
	reg	nli1i;
	reg	nli1l;
	reg	nli1O;
	reg	nliii;
	reg	nliil;
	reg	nliiO;
	reg	nlili;
	reg	nlill;
	reg	nlilO;
	reg	nliOi;
	reg	nlOOOi;
	reg	nlOOOl;
	reg	nlOOOO;
	wire	wire_n0OO_ENA;
	wire	wire_n0i_dataout;
	wire	wire_n0l_dataout;
	wire	wire_n0O_dataout;
	wire	wire_n1i_dataout;
	wire	wire_n1l_dataout;
	wire	wire_n1O_dataout;
	wire	wire_ni_dataout;
	wire	wire_ni0i_dataout;
	wire	wire_ni0l_dataout;
	wire	wire_ni0O_dataout;
	wire	wire_ni1l_dataout;
	wire	wire_ni1O_dataout;
	wire	wire_nii_dataout;
	wire	wire_niii_dataout;
	wire	wire_niil_dataout;
	wire	wire_niiO_dataout;
	wire	wire_nil_dataout;
	wire	wire_nili_dataout;
	wire	wire_nill_dataout;
	wire	wire_niO_dataout;
	wire	wire_niOi_dataout;
	wire	wire_niOl_dataout;
	wire	wire_niOO_dataout;
	wire	wire_nl_dataout;
	wire	wire_nl00i_dataout;
	wire	wire_nl00l_dataout;
	wire	wire_nl00O_dataout;
	wire	wire_nl01O_dataout;
	wire	wire_nl0i_dataout;
	wire	wire_nl0ii_dataout;
	wire	wire_nl0il_dataout;
	wire	wire_nl0iO_dataout;
	wire	wire_nl0l_dataout;
	wire	wire_nl0li_dataout;
	wire	wire_nl0ll_dataout;
	wire	wire_nl0lO_dataout;
	wire	wire_nl0O_dataout;
	wire	wire_nl0Oi_dataout;
	wire	wire_nl1i_dataout;
	wire	wire_nl1l_dataout;
	wire	wire_nl1O_dataout;
	wire	wire_nli_dataout;
	wire	wire_nlii_dataout;
	wire	wire_nlil_dataout;
	wire	wire_nliO_dataout;
	wire	wire_nliOl_dataout;
	wire	wire_nliOO_dataout;
	wire	wire_nll_dataout;
	wire	wire_nll0i_dataout;
	wire	wire_nll0l_dataout;
	wire	wire_nll0O_dataout;
	wire	wire_nll1i_dataout;
	wire	wire_nll1l_dataout;
	wire	wire_nll1O_dataout;
	wire	wire_nlli_dataout;
	wire	wire_nllii_dataout;
	wire	wire_nllil_dataout;
	wire	wire_nlliO_dataout;
	wire	wire_nlll_dataout;
	wire	wire_nllli_dataout;
	wire	wire_nllll_dataout;
	wire	wire_nllO_dataout;
	wire	wire_nlO_dataout;
	wire	wire_nlOi_dataout;
	wire	wire_nlOl_dataout;
	wire	wire_nlOO_dataout;
	wire  [14:0]   wire_n1li_o;
	wire  [7:0]   wire_niO0O_o;
	wire  [5:0]   wire_niOii_o;
	wire  [14:0]   wire_nl0Ol_o;
	wire  [8:0]   wire_nlllO_o;
	wire  [6:0]   wire_nlOll_o;
	wire  [17:0]   wire_nO_o;
	wire  wire_n10i_o;
	wire  wire_n10l_o;
	wire  wire_n10O_o;
	wire  wire_n11i_o;
	wire  wire_n11l_o;
	wire  wire_n11O_o;
	wire  wire_n1ii_o;
	wire  wire_n1il_o;
	wire  wire_n1iO_o;
	wire  wire_ni00l_o;
	wire  wire_ni00O_o;
	wire  wire_ni0ii_o;
	wire  wire_ni0il_o;
	wire  wire_ni0iO_o;
	wire  wire_ni0li_o;
	wire  wire_ni0ll_o;
	wire  wire_ni0lO_o;
	wire  wire_ni0Oi_o;
	wire  wire_ni0Ol_o;
	wire  wire_ni0OO_o;
	wire  wire_nii0i_o;
	wire  wire_nii0l_o;
	wire  wire_nii0O_o;
	wire  wire_nii1i_o;
	wire  wire_nii1l_o;
	wire  wire_nii1O_o;
	wire  wire_niiil_o;
	wire  wire_niiiO_o;
	wire  wire_niiOi_o;
	wire  wire_niiOl_o;
	wire  wire_niiOO_o;
	wire  wire_nil0i_o;
	wire  wire_nil0l_o;
	wire  wire_nil0O_o;
	wire  wire_nil1i_o;
	wire  wire_nil1l_o;
	wire  wire_nil1O_o;
	wire  wire_nilii_o;
	wire  wire_nilil_o;
	wire  wire_niliO_o;
	wire  wire_nilli_o;
	wire  wire_nilll_o;
	wire  wire_nillO_o;
	wire  wire_nilOi_o;
	wire  wire_nilOl_o;
	wire  wire_nilOO_o;
	wire  wire_niO0i_o;
	wire  wire_niO0l_o;
	wire  wire_niO1i_o;
	wire  wire_niO1l_o;
	wire  wire_niO1O_o;
	wire  wire_nllOi_o;
	wire  wire_nllOl_o;
	wire  wire_nllOO_o;
	wire  wire_nlO0i_o;
	wire  wire_nlO0l_o;
	wire  wire_nlO0O_o;
	wire  wire_nlO1i_o;
	wire  wire_nlO1l_o;
	wire  wire_nlO1O_o;
	wire  wire_nlOii_o;
	wire  wire_nlOil_o;
	wire  wire_nlOiO_o;
	wire  wire_nlOli_o;
	wire  wire_nlOlO_o;
	wire  wire_nlOOi_o;
	wire  wire_nlOOl_o;
	wire  wire_nlOOO_o;
	wire  nlOliO;
	wire  nlOlli;
	wire  nlOlll;
	wire  nlOllO;
	wire  nlOlOi;
	wire  nlOlOl;
	wire  nlOlOO;
	wire  nlOO0i;
	wire  nlOO0l;
	wire  nlOO0O;
	wire  nlOO1i;
	wire  nlOO1l;
	wire  nlOO1O;
	wire  nlOOii;
	wire  nlOOil;
	wire  nlOOiO;
	wire  nlOOli;

	initial
	begin
		n000i = 0;
		n000l = 0;
		n000O = 0;
		n001i = 0;
		n001l = 0;
		n001O = 0;
		n00ii = 0;
		n00il = 0;
		n00iO = 0;
		n00li = 0;
		n00ll = 0;
		n00lO = 0;
		n00Oi = 0;
		n00Ol = 0;
		n00OO = 0;
		n010i = 0;
		n010l = 0;
		n010O = 0;
		n011i = 0;
		n011l = 0;
		n011O = 0;
		n01ii = 0;
		n01il = 0;
		n01iO = 0;
		n01li = 0;
		n01ll = 0;
		n01lO = 0;
		n01Oi = 0;
		n01Ol = 0;
		n01OO = 0;
		n0i1i = 0;
		n0i1l = 0;
		n0ii = 0;
		n0il = 0;
		n0iO = 0;
		n0li = 0;
		n0ll = 0;
		n0lO = 0;
		n0Oi = 0;
		n0Ol = 0;
		n100i = 0;
		n100l = 0;
		n100O = 0;
		n101i = 0;
		n101l = 0;
		n101O = 0;
		n10ii = 0;
		n10il = 0;
		n10iO = 0;
		n10li = 0;
		n10ll = 0;
		n10lO = 0;
		n10Oi = 0;
		n10Ol = 0;
		n10OO = 0;
		n110i = 0;
		n110l = 0;
		n110O = 0;
		n111i = 0;
		n111l = 0;
		n111O = 0;
		n11ii = 0;
		n11il = 0;
		n11iO = 0;
		n11li = 0;
		n11ll = 0;
		n11lO = 0;
		n11Oi = 0;
		n11Ol = 0;
		n11OO = 0;
		n1i0i = 0;
		n1i0l = 0;
		n1i0O = 0;
		n1i1i = 0;
		n1i1l = 0;
		n1i1O = 0;
		n1iii = 0;
		n1iil = 0;
		n1iiO = 0;
		n1ili = 0;
		n1ill = 0;
		n1ilO = 0;
		n1iOi = 0;
		n1iOl = 0;
		n1iOO = 0;
		n1l0i = 0;
		n1l0l = 0;
		n1l0O = 0;
		n1l1i = 0;
		n1l1l = 0;
		n1l1O = 0;
		n1lii = 0;
		n1lil = 0;
		n1liO = 0;
		n1lli = 0;
		n1lll = 0;
		n1llO = 0;
		n1lOi = 0;
		n1lOl = 0;
		n1lOO = 0;
		n1O0i = 0;
		n1O0l = 0;
		n1O0O = 0;
		n1O1i = 0;
		n1O1l = 0;
		n1O1O = 0;
		n1Oii = 0;
		n1Oil = 0;
		n1OiO = 0;
		n1Oli = 0;
		n1Oll = 0;
		n1OlO = 0;
		n1OOi = 0;
		n1OOl = 0;
		n1OOO = 0;
		ni1i = 0;
		niiii = 0;
		niilO = 0;
		nl0OO = 0;
		nli0i = 0;
		nli0l = 0;
		nli0O = 0;
		nli1i = 0;
		nli1l = 0;
		nli1O = 0;
		nliii = 0;
		nliil = 0;
		nliiO = 0;
		nlili = 0;
		nlill = 0;
		nlilO = 0;
		nliOi = 0;
		nlOOOi = 0;
		nlOOOl = 0;
		nlOOOO = 0;
	end
	always @ ( posedge clk or  posedge areset)
	begin
		if (areset == 1'b1) 
		begin
			n000i <= 0;
			n000l <= 0;
			n000O <= 0;
			n001i <= 0;
			n001l <= 0;
			n001O <= 0;
			n00ii <= 0;
			n00il <= 0;
			n00iO <= 0;
			n00li <= 0;
			n00ll <= 0;
			n00lO <= 0;
			n00Oi <= 0;
			n00Ol <= 0;
			n00OO <= 0;
			n010i <= 0;
			n010l <= 0;
			n010O <= 0;
			n011i <= 0;
			n011l <= 0;
			n011O <= 0;
			n01ii <= 0;
			n01il <= 0;
			n01iO <= 0;
			n01li <= 0;
			n01ll <= 0;
			n01lO <= 0;
			n01Oi <= 0;
			n01Ol <= 0;
			n01OO <= 0;
			n0i1i <= 0;
			n0i1l <= 0;
			n0ii <= 0;
			n0il <= 0;
			n0iO <= 0;
			n0li <= 0;
			n0ll <= 0;
			n0lO <= 0;
			n0Oi <= 0;
			n0Ol <= 0;
			n100i <= 0;
			n100l <= 0;
			n100O <= 0;
			n101i <= 0;
			n101l <= 0;
			n101O <= 0;
			n10ii <= 0;
			n10il <= 0;
			n10iO <= 0;
			n10li <= 0;
			n10ll <= 0;
			n10lO <= 0;
			n10Oi <= 0;
			n10Ol <= 0;
			n10OO <= 0;
			n110i <= 0;
			n110l <= 0;
			n110O <= 0;
			n111i <= 0;
			n111l <= 0;
			n111O <= 0;
			n11ii <= 0;
			n11il <= 0;
			n11iO <= 0;
			n11li <= 0;
			n11ll <= 0;
			n11lO <= 0;
			n11Oi <= 0;
			n11Ol <= 0;
			n11OO <= 0;
			n1i0i <= 0;
			n1i0l <= 0;
			n1i0O <= 0;
			n1i1i <= 0;
			n1i1l <= 0;
			n1i1O <= 0;
			n1iii <= 0;
			n1iil <= 0;
			n1iiO <= 0;
			n1ili <= 0;
			n1ill <= 0;
			n1ilO <= 0;
			n1iOi <= 0;
			n1iOl <= 0;
			n1iOO <= 0;
			n1l0i <= 0;
			n1l0l <= 0;
			n1l0O <= 0;
			n1l1i <= 0;
			n1l1l <= 0;
			n1l1O <= 0;
			n1lii <= 0;
			n1lil <= 0;
			n1liO <= 0;
			n1lli <= 0;
			n1lll <= 0;
			n1llO <= 0;
			n1lOi <= 0;
			n1lOl <= 0;
			n1lOO <= 0;
			n1O0i <= 0;
			n1O0l <= 0;
			n1O0O <= 0;
			n1O1i <= 0;
			n1O1l <= 0;
			n1O1O <= 0;
			n1Oii <= 0;
			n1Oil <= 0;
			n1OiO <= 0;
			n1Oli <= 0;
			n1Oll <= 0;
			n1OlO <= 0;
			n1OOi <= 0;
			n1OOl <= 0;
			n1OOO <= 0;
			ni1i <= 0;
			niiii <= 0;
			niilO <= 0;
			nl0OO <= 0;
			nli0i <= 0;
			nli0l <= 0;
			nli0O <= 0;
			nli1i <= 0;
			nli1l <= 0;
			nli1O <= 0;
			nliii <= 0;
			nliil <= 0;
			nliiO <= 0;
			nlili <= 0;
			nlill <= 0;
			nlilO <= 0;
			nliOi <= 0;
			nlOOOi <= 0;
			nlOOOl <= 0;
			nlOOOO <= 0;
		end
		else if  (wire_n0OO_ENA == 1'b1) 
		begin
			n000i <= wire_nil1l_o;
			n000l <= wire_nil1O_o;
			n000O <= wire_nil0i_o;
			n001i <= wire_niiOl_o;
			n001l <= wire_niiOO_o;
			n001O <= wire_nil1i_o;
			n00ii <= wire_nil0l_o;
			n00il <= wire_nil0O_o;
			n00iO <= wire_nilii_o;
			n00li <= wire_niO0O_o[1];
			n00ll <= wire_niO0O_o[2];
			n00lO <= wire_niO0O_o[3];
			n00Oi <= wire_niO0O_o[4];
			n00Ol <= wire_niO0O_o[5];
			n00OO <= wire_niO0O_o[6];
			n010i <= wire_nl0Ol_o[2];
			n010l <= wire_nl0Ol_o[3];
			n010O <= wire_nl0Ol_o[4];
			n011i <= wire_nl0Ol_o[4];
			n011l <= wire_nl0Ol_o[0];
			n011O <= wire_nl0Ol_o[1];
			n01ii <= wire_nl0Ol_o[5];
			n01il <= wire_nl0Ol_o[6];
			n01iO <= wire_nl0Ol_o[7];
			n01li <= wire_nl0Ol_o[8];
			n01ll <= wire_nl0Ol_o[9];
			n01lO <= wire_nl0Ol_o[10];
			n01Oi <= wire_nl0Ol_o[11];
			n01Ol <= wire_nl0Ol_o[12];
			n01OO <= wire_niiOi_o;
			n0i1i <= wire_niO0O_o[7];
			n0i1l <= nlOlOl;
			n0ii <= wire_ni1O_dataout;
			n0il <= wire_ni0i_dataout;
			n0iO <= wire_ni0l_dataout;
			n0li <= wire_ni0O_dataout;
			n0ll <= wire_niii_dataout;
			n0lO <= wire_niil_dataout;
			n0Oi <= wire_niiO_dataout;
			n0Ol <= wire_nili_dataout;
			n100i <= n10Ol;
			n100l <= wire_niOi_dataout;
			n100O <= wire_niOl_dataout;
			n101i <= n10ll;
			n101l <= n10lO;
			n101O <= n10Oi;
			n10ii <= wire_niOO_dataout;
			n10il <= wire_nl1i_dataout;
			n10iO <= wire_nl1l_dataout;
			n10li <= wire_nl1O_dataout;
			n10ll <= wire_nl0i_dataout;
			n10lO <= wire_nl0l_dataout;
			n10Oi <= wire_nl0O_dataout;
			n10Ol <= wire_nlii_dataout;
			n10OO <= nlOOil;
			n110i <= wire_ni_dataout;
			n110l <= wire_nlil_dataout;
			n110O <= wire_nliO_dataout;
			n111i <= wire_nli_dataout;
			n111l <= wire_nll_dataout;
			n111O <= wire_nlO_dataout;
			n11ii <= wire_nlli_dataout;
			n11il <= wire_nlll_dataout;
			n11iO <= wire_nllO_dataout;
			n11li <= n100l;
			n11ll <= n100O;
			n11lO <= n10ii;
			n11Oi <= n10il;
			n11Ol <= n10iO;
			n11OO <= n10li;
			n1i0i <= wire_nl0iO_dataout;
			n1i0l <= wire_nl0ll_dataout;
			n1i0O <= wire_nl0lO_dataout;
			n1i1i <= ((((~ wire_nl0Oi_dataout) & (~ wire_nl0lO_dataout)) & (~ wire_nl0ll_dataout)) & (~ wire_nl0li_dataout));
			n1i1l <= wire_nl0ii_dataout;
			n1i1O <= wire_nl0il_dataout;
			n1iii <= wire_nl0Oi_dataout;
			n1iil <= n1iiO;
			n1iiO <= n1ili;
			n1ili <= wire_nlOi_dataout;
			n1ill <= nlOlll;
			n1ilO <= n1ill;
			n1iOi <= n1iOl;
			n1iOl <= (~ nlOOOl);
			n1iOO <= n1l0l;
			n1l0i <= n1liO;
			n1l0l <= n110l;
			n1l0O <= n110O;
			n1l1i <= n1l0O;
			n1l1l <= n1lii;
			n1l1O <= n1lil;
			n1lii <= n11ii;
			n1lil <= n11il;
			n1liO <= n11iO;
			n1lli <= n1lll;
			n1lll <= n1llO;
			n1llO <= wire_nl_dataout;
			n1lOi <= n1lOl;
			n1lOl <= nlOOOl;
			n1lOO <= nlOlli;
			n1O0i <= ((((nlOO0O & nlOO1O) & n1iil) & (~ nlOllO)) | (((((nlOO0i & n1lOi) & n1iil) & n1lli) | ((nlOO1O & n1lOi) & n1iil)) | ((nlOO1l & n1lli) | (nlOO1i & n1iil))));
			n1O0l <= (n1ilO & (~ n1O1i));
			n1O0O <= (nlOO0l & (~ n1O1O));
			n1O1i <= n1O1l;
			n1O1l <= n1lOO;
			n1O1O <= nlOliO;
			n1Oii <= n1Oil;
			n1Oil <= n1OiO;
			n1OiO <= nlOOOi;
			n1Oli <= nlOO1l;
			n1Oll <= nlOO1i;
			n1OlO <= wire_nl0Ol_o[0];
			n1OOi <= wire_nl0Ol_o[1];
			n1OOl <= wire_nl0Ol_o[2];
			n1OOO <= wire_nl0Ol_o[3];
			ni1i <= wire_nill_dataout;
			niiii <= wire_nliOl_dataout;
			niilO <= wire_niiil_o;
			nl0OO <= wire_nliOO_dataout;
			nli0i <= wire_nll0i_dataout;
			nli0l <= wire_nll0l_dataout;
			nli0O <= wire_nll0O_dataout;
			nli1i <= wire_nll1i_dataout;
			nli1l <= wire_nll1l_dataout;
			nli1O <= wire_nll1O_dataout;
			nliii <= wire_nllii_dataout;
			nliil <= wire_nllil_dataout;
			nliiO <= wire_nlliO_dataout;
			nlili <= wire_nllli_dataout;
			nlill <= wire_nllll_dataout;
			nlilO <= wire_n1li_o[13];
			nliOi <= wire_ni1l_dataout;
			nlOOOi <= (wire_nl_dataout ^ wire_nlOi_dataout);
			nlOOOl <= nlOOli;
			nlOOOO <= wire_niO_dataout;
		end
	end
	assign
		wire_n0OO_ENA = en[0];
	assign		wire_n0i_dataout = (wire_nO_o[17] === 1'b1) ? a[5] : b[5];
	assign		wire_n0l_dataout = (wire_nO_o[17] === 1'b1) ? a[6] : b[6];
	assign		wire_n0O_dataout = (wire_nO_o[17] === 1'b1) ? a[7] : b[7];
	assign		wire_n1i_dataout = (wire_nO_o[17] === 1'b1) ? a[2] : b[2];
	assign		wire_n1l_dataout = (wire_nO_o[17] === 1'b1) ? a[3] : b[3];
	assign		wire_n1O_dataout = (wire_nO_o[17] === 1'b1) ? a[4] : b[4];
	assign		wire_ni_dataout = (wire_nO_o[17] === 1'b1) ? a[14] : b[14];
	and(wire_ni0i_dataout, wire_n1i_dataout, (~ nlOOli));
	and(wire_ni0l_dataout, wire_n1l_dataout, (~ nlOOli));
	and(wire_ni0O_dataout, wire_n1O_dataout, (~ nlOOli));
	and(wire_ni1l_dataout, wire_nlOl_dataout, (~ nlOOli));
	and(wire_ni1O_dataout, wire_nlOO_dataout, (~ nlOOli));
	assign		wire_nii_dataout = (wire_nO_o[17] === 1'b1) ? a[8] : b[8];
	and(wire_niii_dataout, wire_n0i_dataout, (~ nlOOli));
	and(wire_niil_dataout, wire_n0l_dataout, (~ nlOOli));
	and(wire_niiO_dataout, wire_n0O_dataout, (~ nlOOli));
	assign		wire_nil_dataout = (wire_nO_o[17] === 1'b1) ? a[9] : b[9];
	and(wire_nili_dataout, wire_nii_dataout, (~ nlOOli));
	and(wire_nill_dataout, wire_nil_dataout, (~ nlOOli));
	assign		wire_niO_dataout = (wire_nO_o[17] === 1'b1) ? a[10] : b[10];
	assign		wire_niOi_dataout = (wire_nO_o[17] === 1'b1) ? b[0] : a[0];
	assign		wire_niOl_dataout = (wire_nO_o[17] === 1'b1) ? b[1] : a[1];
	assign		wire_niOO_dataout = (wire_nO_o[17] === 1'b1) ? b[2] : a[2];
	assign		wire_nl_dataout = (wire_nO_o[17] === 1'b1) ? a[15] : b[15];
	assign		wire_nl00i_dataout = ((~ n1i1i) === 1'b1) ? n1i0l : n1i1l;
	assign		wire_nl00l_dataout = ((~ n1i1i) === 1'b1) ? n1i0O : n1i1O;
	assign		wire_nl00O_dataout = ((~ n1i1i) === 1'b1) ? n1iii : n1i0i;
	assign		wire_nl01O_dataout = ((~ nlOOii) === 1'b1) ? wire_nl00O_dataout : wire_nl00i_dataout;
	assign		wire_nl0i_dataout = (wire_nO_o[17] === 1'b1) ? b[6] : a[6];
	or(wire_nl0ii_dataout, wire_nl0Ol_o[7], ~((~ nlOOil)));
	assign		wire_nl0il_dataout = ((~ nlOOil) === 1'b1) ? wire_nl0Ol_o[8] : wire_nl0Ol_o[0];
	assign		wire_nl0iO_dataout = ((~ nlOOil) === 1'b1) ? wire_nl0Ol_o[9] : wire_nl0Ol_o[1];
	assign		wire_nl0l_dataout = (wire_nO_o[17] === 1'b1) ? b[7] : a[7];
	assign		wire_nl0li_dataout = ((~ nlOOil) === 1'b1) ? wire_nl0Ol_o[10] : wire_nl0Ol_o[2];
	assign		wire_nl0ll_dataout = ((~ nlOOil) === 1'b1) ? wire_nl0Ol_o[11] : wire_nl0Ol_o[3];
	assign		wire_nl0lO_dataout = ((~ nlOOil) === 1'b1) ? wire_nl0Ol_o[12] : wire_nl0Ol_o[4];
	assign		wire_nl0O_dataout = (wire_nO_o[17] === 1'b1) ? b[8] : a[8];
	assign		wire_nl0Oi_dataout = ((~ nlOOil) === 1'b1) ? wire_nl0Ol_o[13] : wire_nl0Ol_o[5];
	assign		wire_nl1i_dataout = (wire_nO_o[17] === 1'b1) ? b[3] : a[3];
	assign		wire_nl1l_dataout = (wire_nO_o[17] === 1'b1) ? b[4] : a[4];
	assign		wire_nl1O_dataout = (wire_nO_o[17] === 1'b1) ? b[5] : a[5];
	assign		wire_nli_dataout = (wire_nO_o[17] === 1'b1) ? a[11] : b[11];
	assign		wire_nlii_dataout = (wire_nO_o[17] === 1'b1) ? b[9] : a[9];
	assign		wire_nlil_dataout = (wire_nO_o[17] === 1'b1) ? b[10] : a[10];
	assign		wire_nliO_dataout = (wire_nO_o[17] === 1'b1) ? b[11] : a[11];
	assign		wire_nliOl_dataout = (wire_nlllO_o[8] === 1'b1) ? wire_nllOi_o : wire_n1li_o[13];
	assign		wire_nliOO_dataout = (wire_nlllO_o[8] === 1'b1) ? wire_nllOl_o : wire_n1li_o[13];
	assign		wire_nll_dataout = (wire_nO_o[17] === 1'b1) ? a[12] : b[12];
	assign		wire_nll0i_dataout = (wire_nlllO_o[8] === 1'b1) ? wire_nlO1O_o : wire_n1li_o[13];
	assign		wire_nll0l_dataout = (wire_nlllO_o[8] === 1'b1) ? wire_nlO0i_o : wire_n1li_o[13];
	assign		wire_nll0O_dataout = (wire_nlllO_o[8] === 1'b1) ? wire_nlO0l_o : wire_n1li_o[13];
	assign		wire_nll1i_dataout = (wire_nlllO_o[8] === 1'b1) ? wire_nllOO_o : wire_n1li_o[13];
	assign		wire_nll1l_dataout = (wire_nlllO_o[8] === 1'b1) ? wire_nlO1i_o : wire_n1li_o[13];
	assign		wire_nll1O_dataout = (wire_nlllO_o[8] === 1'b1) ? wire_nlO1l_o : wire_n1li_o[13];
	assign		wire_nlli_dataout = (wire_nO_o[17] === 1'b1) ? b[12] : a[12];
	assign		wire_nllii_dataout = (wire_nlllO_o[8] === 1'b1) ? wire_nlO0O_o : wire_n1li_o[13];
	assign		wire_nllil_dataout = (wire_nlllO_o[8] === 1'b1) ? wire_nlOii_o : wire_n1li_o[13];
	assign		wire_nlliO_dataout = (wire_nlllO_o[8] === 1'b1) ? wire_nlOil_o : wire_n1li_o[13];
	assign		wire_nlll_dataout = (wire_nO_o[17] === 1'b1) ? b[13] : a[13];
	assign		wire_nllli_dataout = (wire_nlllO_o[8] === 1'b1) ? wire_nlOiO_o : wire_n1li_o[13];
	assign		wire_nllll_dataout = (wire_nlllO_o[8] === 1'b1) ? wire_nlOli_o : wire_n1li_o[13];
	assign		wire_nllO_dataout = (wire_nO_o[17] === 1'b1) ? b[14] : a[14];
	assign		wire_nlO_dataout = (wire_nO_o[17] === 1'b1) ? a[13] : b[13];
	assign		wire_nlOi_dataout = (wire_nO_o[17] === 1'b1) ? b[15] : a[15];
	assign		wire_nlOl_dataout = (wire_nO_o[17] === 1'b1) ? a[0] : b[0];
	assign		wire_nlOO_dataout = (wire_nO_o[17] === 1'b1) ? a[1] : b[1];
	oper_add   n1li
	( 
	.a({1'b0, nlOOOi, (nlOOOi ^ (~ nlOOOl)), (ni1i ^ nlOOOi), (n0Ol ^ nlOOOi), (n0Oi ^ nlOOOi), (n0lO ^ nlOOOi), (n0ll ^ nlOOOi), (n0li ^ nlOOOi), (n0iO ^ nlOOOi), (n0il ^ nlOOOi), (n0ii ^ nlOOOi), (nliOi ^ nlOOOi), {2{nlOOOi}}}),
	.b({{14{1'b0}}, nlOOOi}),
	.cin(1'b0),
	.cout(),
	.o(wire_n1li_o));
	defparam
		n1li.sgate_representation = 0,
		n1li.width_a = 15,
		n1li.width_b = 15,
		n1li.width_o = 15;
	oper_add   niO0O
	( 
	.a({1'b0, wire_niOii_o[5:0], 1'b1}),
	.b({{3{1'b1}}, (~ n10OO), (~ n1i1i), (~ nlOOii), wire_nl01O_dataout, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_niO0O_o));
	defparam
		niO0O.sgate_representation = 0,
		niO0O.width_a = 8,
		niO0O.width_b = 8,
		niO0O.width_o = 8;
	oper_add   niOii
	( 
	.a({1'b0, n1l0i, n1l1O, n1l1l, n1l1i, n1iOO}),
	.b({{5{1'b0}}, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_niOii_o));
	defparam
		niOii.sgate_representation = 0,
		niOii.width_a = 6,
		niOii.width_b = 6,
		niOii.width_o = 6;
	oper_add   nl0Ol
	( 
	.a({{2{1'b0}}, 1'b1, n100i, n101O, n101l, n101i, n11OO, n11Ol, n11Oi, n11lO, n11ll, n11li, {2{1'b0}}}),
	.b({{2{nlilO}}, nlill, nlili, nliiO, nliil, nliii, nli0O, nli0l, nli0i, nli1O, nli1l, nli1i, nl0OO, niiii}),
	.cin(1'b0),
	.cout(),
	.o(wire_nl0Ol_o));
	defparam
		nl0Ol.sgate_representation = 0,
		nl0Ol.width_a = 15,
		nl0Ol.width_b = 15,
		nl0Ol.width_o = 15;
	oper_add   nlllO
	( 
	.a({{2{1'b0}}, wire_nlOll_o[6:1], 1'b1}),
	.b({{4{1'b1}}, {3{1'b0}}, {2{1'b1}}}),
	.cin(1'b0),
	.cout(),
	.o(wire_nlllO_o));
	defparam
		nlllO.sgate_representation = 0,
		nlllO.width_a = 9,
		nlllO.width_b = 9,
		nlllO.width_o = 9;
	oper_add   nlOll
	( 
	.a({1'b0, n11iO, n11il, n11ii, n110O, n110l, 1'b1}),
	.b({1'b1, (~ n110i), (~ n111O), (~ n111l), (~ n111i), (~ nlOOOO), 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_nlOll_o));
	defparam
		nlOll.sgate_representation = 0,
		nlOll.width_a = 7,
		nlOll.width_b = 7,
		nlOll.width_o = 7;
	oper_add   nO
	( 
	.a({{2{1'b0}}, a[14:0], 1'b1}),
	.b({{2{1'b1}}, (~ b[14]), (~ b[13]), (~ b[12]), (~ b[11]), (~ b[10]), (~ b[9]), (~ b[8]), (~ b[7]), (~ b[6]), (~ b[5]), (~ b[4]), (~ b[3]), (~ b[2]), (~ b[1]), (~ b[0]), 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_nO_o));
	defparam
		nO.sgate_representation = 0,
		nO.width_a = 18,
		nO.width_b = 18,
		nO.width_o = 18;
	oper_mux   n10i
	( 
	.data({{2{wire_n1li_o[13]}}, wire_n1li_o[11], wire_n1li_o[7]}),
	.o(wire_n10i_o),
	.sel({wire_nlOll_o[4:3]}));
	defparam
		n10i.width_data = 4,
		n10i.width_sel = 2;
	oper_mux   n10l
	( 
	.data({wire_n1li_o[13], wire_n1li_o[13:12], wire_n1li_o[8]}),
	.o(wire_n10l_o),
	.sel({wire_nlOll_o[4:3]}));
	defparam
		n10l.width_data = 4,
		n10l.width_sel = 2;
	oper_mux   n10O
	( 
	.data({{3{wire_n1li_o[13]}}, wire_n1li_o[9]}),
	.o(wire_n10O_o),
	.sel({wire_nlOll_o[4:3]}));
	defparam
		n10O.width_data = 4,
		n10O.width_sel = 2;
	oper_mux   n11i
	( 
	.data({wire_n1li_o[13:12], wire_n1li_o[8], wire_n1li_o[4]}),
	.o(wire_n11i_o),
	.sel({wire_nlOll_o[4:3]}));
	defparam
		n11i.width_data = 4,
		n11i.width_sel = 2;
	oper_mux   n11l
	( 
	.data({{2{wire_n1li_o[13]}}, wire_n1li_o[9], wire_n1li_o[5]}),
	.o(wire_n11l_o),
	.sel({wire_nlOll_o[4:3]}));
	defparam
		n11l.width_data = 4,
		n11l.width_sel = 2;
	oper_mux   n11O
	( 
	.data({{2{wire_n1li_o[13]}}, wire_n1li_o[10], wire_n1li_o[6]}),
	.o(wire_n11O_o),
	.sel({wire_nlOll_o[4:3]}));
	defparam
		n11O.width_data = 4,
		n11O.width_sel = 2;
	oper_mux   n1ii
	( 
	.data({{3{wire_n1li_o[13]}}, wire_n1li_o[10]}),
	.o(wire_n1ii_o),
	.sel({wire_nlOll_o[4:3]}));
	defparam
		n1ii.width_data = 4,
		n1ii.width_sel = 2;
	oper_mux   n1il
	( 
	.data({{3{wire_n1li_o[13]}}, wire_n1li_o[11]}),
	.o(wire_n1il_o),
	.sel({wire_nlOll_o[4:3]}));
	defparam
		n1il.width_data = 4,
		n1il.width_sel = 2;
	oper_mux   n1iO
	( 
	.data({{2{wire_n1li_o[13]}}, wire_n1li_o[13:12]}),
	.o(wire_n1iO_o),
	.sel({wire_nlOll_o[4:3]}));
	defparam
		n1iO.width_data = 4,
		n1iO.width_sel = 2;
	oper_mux   ni00l
	( 
	.data({1'b1, 1'b0, n01OO, 1'b0}),
	.o(wire_ni00l_o),
	.sel({wire_nii0O_o, wire_nii0l_o}));
	defparam
		ni00l.width_data = 4,
		ni00l.width_sel = 2;
	oper_mux   ni00O
	( 
	.data({{2{1'b0}}, n001i, 1'b0}),
	.o(wire_ni00O_o),
	.sel({wire_nii0O_o, wire_nii0l_o}));
	defparam
		ni00O.width_data = 4,
		ni00O.width_sel = 2;
	oper_mux   ni0ii
	( 
	.data({{2{1'b0}}, n001l, 1'b0}),
	.o(wire_ni0ii_o),
	.sel({wire_nii0O_o, wire_nii0l_o}));
	defparam
		ni0ii.width_data = 4,
		ni0ii.width_sel = 2;
	oper_mux   ni0il
	( 
	.data({{2{1'b0}}, n001O, 1'b0}),
	.o(wire_ni0il_o),
	.sel({wire_nii0O_o, wire_nii0l_o}));
	defparam
		ni0il.width_data = 4,
		ni0il.width_sel = 2;
	oper_mux   ni0iO
	( 
	.data({{2{1'b0}}, n000i, 1'b0}),
	.o(wire_ni0iO_o),
	.sel({wire_nii0O_o, wire_nii0l_o}));
	defparam
		ni0iO.width_data = 4,
		ni0iO.width_sel = 2;
	oper_mux   ni0li
	( 
	.data({{2{1'b0}}, n000l, 1'b0}),
	.o(wire_ni0li_o),
	.sel({wire_nii0O_o, wire_nii0l_o}));
	defparam
		ni0li.width_data = 4,
		ni0li.width_sel = 2;
	oper_mux   ni0ll
	( 
	.data({{2{1'b0}}, n000O, 1'b0}),
	.o(wire_ni0ll_o),
	.sel({wire_nii0O_o, wire_nii0l_o}));
	defparam
		ni0ll.width_data = 4,
		ni0ll.width_sel = 2;
	oper_mux   ni0lO
	( 
	.data({{2{1'b0}}, n00ii, 1'b0}),
	.o(wire_ni0lO_o),
	.sel({wire_nii0O_o, wire_nii0l_o}));
	defparam
		ni0lO.width_data = 4,
		ni0lO.width_sel = 2;
	oper_mux   ni0Oi
	( 
	.data({{2{1'b0}}, n00il, 1'b0}),
	.o(wire_ni0Oi_o),
	.sel({wire_nii0O_o, wire_nii0l_o}));
	defparam
		ni0Oi.width_data = 4,
		ni0Oi.width_sel = 2;
	oper_mux   ni0Ol
	( 
	.data({{2{1'b0}}, n00iO, 1'b0}),
	.o(wire_ni0Ol_o),
	.sel({wire_nii0O_o, wire_nii0l_o}));
	defparam
		ni0Ol.width_data = 4,
		ni0Ol.width_sel = 2;
	oper_mux   ni0OO
	( 
	.data({{2{1'b1}}, n00li, 1'b0}),
	.o(wire_ni0OO_o),
	.sel({wire_nii0O_o, wire_nii0l_o}));
	defparam
		ni0OO.width_data = 4,
		ni0OO.width_sel = 2;
	oper_mux   nii0i
	( 
	.data({{2{1'b1}}, n00Ol, 1'b0}),
	.o(wire_nii0i_o),
	.sel({wire_nii0O_o, wire_nii0l_o}));
	defparam
		nii0i.width_data = 4,
		nii0i.width_sel = 2;
	oper_mux   nii0l
	( 
	.data({{4{1'b1}}, {3{1'b0}}, 1'b1}),
	.o(wire_nii0l_o),
	.sel({nlOlOO, wire_niiiO_o, niilO}));
	defparam
		nii0l.width_data = 8,
		nii0l.width_sel = 3;
	oper_mux   nii0O
	( 
	.data({{3{1'b1}}, 1'b0}),
	.o(wire_nii0O_o),
	.sel({nlOlOO, wire_niiiO_o}));
	defparam
		nii0O.width_data = 4,
		nii0O.width_sel = 2;
	oper_mux   nii1i
	( 
	.data({{2{1'b1}}, n00ll, 1'b0}),
	.o(wire_nii1i_o),
	.sel({wire_nii0O_o, wire_nii0l_o}));
	defparam
		nii1i.width_data = 4,
		nii1i.width_sel = 2;
	oper_mux   nii1l
	( 
	.data({{2{1'b1}}, n00lO, 1'b0}),
	.o(wire_nii1l_o),
	.sel({wire_nii0O_o, wire_nii0l_o}));
	defparam
		nii1l.width_data = 4,
		nii1l.width_sel = 2;
	oper_mux   nii1O
	( 
	.data({{2{1'b1}}, n00Oi, 1'b0}),
	.o(wire_nii1O_o),
	.sel({wire_nii0O_o, wire_nii0l_o}));
	defparam
		nii1O.width_data = 4,
		nii1O.width_sel = 2;
	oper_mux   niiil
	( 
	.data({{3{1'b0}}, {2{1'b1}}, {6{1'b0}}, {2{1'b1}}, {6{1'b0}}, {2{1'b1}}, {7{1'b0}}, 1'b1, {3{1'b0}}}),
	.o(wire_niiil_o),
	.sel({nlOllO, wire_niO0O_o[7], nlOlOl, n1lOi, nlOO0i}));
	defparam
		niiil.width_data = 32,
		niiil.width_sel = 5;
	oper_mux   niiiO
	( 
	.data({{31{1'b0}}, 1'b1, {25{1'b0}}, {5{1'b1}}, {2{1'b0}}}),
	.o(wire_niiiO_o),
	.sel({(nlOlOi & n0i1l), n1O0l, n1O0O, n1Oli, n1Oll, n1Oii}));
	defparam
		niiiO.width_data = 64,
		niiiO.width_sel = 6;
	oper_mux   niiOi
	( 
	.data({wire_niliO_o, wire_nilil_o, wire_nilll_o, wire_nilli_o}),
	.o(wire_niiOi_o),
	.sel({nlOOii, wire_nl01O_dataout}));
	defparam
		niiOi.width_data = 4,
		niiOi.width_sel = 2;
	oper_mux   niiOl
	( 
	.data({wire_nilli_o, wire_niliO_o, wire_nillO_o, wire_nilll_o}),
	.o(wire_niiOl_o),
	.sel({nlOOii, wire_nl01O_dataout}));
	defparam
		niiOl.width_data = 4,
		niiOl.width_sel = 2;
	oper_mux   niiOO
	( 
	.data({wire_nilll_o, wire_nilli_o, wire_nilOi_o, wire_nillO_o}),
	.o(wire_niiOO_o),
	.sel({nlOOii, wire_nl01O_dataout}));
	defparam
		niiOO.width_data = 4,
		niiOO.width_sel = 2;
	oper_mux   nil0i
	( 
	.data({wire_nilOO_o, wire_nilOl_o, wire_niO1l_o, wire_niO1i_o}),
	.o(wire_nil0i_o),
	.sel({nlOOii, wire_nl01O_dataout}));
	defparam
		nil0i.width_data = 4,
		nil0i.width_sel = 2;
	oper_mux   nil0l
	( 
	.data({wire_niO1i_o, wire_nilOO_o, wire_niO1O_o, wire_niO1l_o}),
	.o(wire_nil0l_o),
	.sel({nlOOii, wire_nl01O_dataout}));
	defparam
		nil0l.width_data = 4,
		nil0l.width_sel = 2;
	oper_mux   nil0O
	( 
	.data({wire_niO1l_o, wire_niO1i_o, wire_niO0i_o, wire_niO1O_o}),
	.o(wire_nil0O_o),
	.sel({nlOOii, wire_nl01O_dataout}));
	defparam
		nil0O.width_data = 4,
		nil0O.width_sel = 2;
	oper_mux   nil1i
	( 
	.data({wire_nillO_o, wire_nilll_o, wire_nilOl_o, wire_nilOi_o}),
	.o(wire_nil1i_o),
	.sel({nlOOii, wire_nl01O_dataout}));
	defparam
		nil1i.width_data = 4,
		nil1i.width_sel = 2;
	oper_mux   nil1l
	( 
	.data({wire_nilOi_o, wire_nillO_o, wire_nilOO_o, wire_nilOl_o}),
	.o(wire_nil1l_o),
	.sel({nlOOii, wire_nl01O_dataout}));
	defparam
		nil1l.width_data = 4,
		nil1l.width_sel = 2;
	oper_mux   nil1O
	( 
	.data({wire_nilOl_o, wire_nilOi_o, wire_niO1i_o, wire_nilOO_o}),
	.o(wire_nil1O_o),
	.sel({nlOOii, wire_nl01O_dataout}));
	defparam
		nil1O.width_data = 4,
		nil1O.width_sel = 2;
	oper_mux   nilii
	( 
	.data({wire_niO1O_o, wire_niO1l_o, wire_niO0l_o, wire_niO0i_o}),
	.o(wire_nilii_o),
	.sel({nlOOii, wire_nl01O_dataout}));
	defparam
		nilii.width_data = 4,
		nilii.width_sel = 2;
	oper_mux   nilil
	( 
	.data({{3{1'b0}}, n011l}),
	.o(wire_nilil_o),
	.sel({n10OO, n1i1i}));
	defparam
		nilil.width_data = 4,
		nilil.width_sel = 2;
	oper_mux   niliO
	( 
	.data({{3{1'b0}}, n011O}),
	.o(wire_niliO_o),
	.sel({n10OO, n1i1i}));
	defparam
		niliO.width_data = 4,
		niliO.width_sel = 2;
	oper_mux   nilli
	( 
	.data({{3{1'b0}}, n010i}),
	.o(wire_nilli_o),
	.sel({n10OO, n1i1i}));
	defparam
		nilli.width_data = 4,
		nilli.width_sel = 2;
	oper_mux   nilll
	( 
	.data({{3{1'b0}}, n010l}),
	.o(wire_nilll_o),
	.sel({n10OO, n1i1i}));
	defparam
		nilll.width_data = 4,
		nilll.width_sel = 2;
	oper_mux   nillO
	( 
	.data({{2{1'b0}}, n011l, n010O}),
	.o(wire_nillO_o),
	.sel({n10OO, n1i1i}));
	defparam
		nillO.width_data = 4,
		nillO.width_sel = 2;
	oper_mux   nilOi
	( 
	.data({{2{1'b0}}, n011O, n01ii}),
	.o(wire_nilOi_o),
	.sel({n10OO, n1i1i}));
	defparam
		nilOi.width_data = 4,
		nilOi.width_sel = 2;
	oper_mux   nilOl
	( 
	.data({{2{1'b0}}, n010i, n01il}),
	.o(wire_nilOl_o),
	.sel({n10OO, n1i1i}));
	defparam
		nilOl.width_data = 4,
		nilOl.width_sel = 2;
	oper_mux   nilOO
	( 
	.data({{2{1'b0}}, n010l, n01iO}),
	.o(wire_nilOO_o),
	.sel({n10OO, n1i1i}));
	defparam
		nilOO.width_data = 4,
		nilOO.width_sel = 2;
	oper_mux   niO0i
	( 
	.data({1'b0, n1OOO, n01iO, n01Oi}),
	.o(wire_niO0i_o),
	.sel({n10OO, n1i1i}));
	defparam
		niO0i.width_data = 4,
		niO0i.width_sel = 2;
	oper_mux   niO0l
	( 
	.data({n011l, n011i, n01li, n01Ol}),
	.o(wire_niO0l_o),
	.sel({n10OO, n1i1i}));
	defparam
		niO0l.width_data = 4,
		niO0l.width_sel = 2;
	oper_mux   niO1i
	( 
	.data({1'b0, n1OlO, n010O, n01li}),
	.o(wire_niO1i_o),
	.sel({n10OO, n1i1i}));
	defparam
		niO1i.width_data = 4,
		niO1i.width_sel = 2;
	oper_mux   niO1l
	( 
	.data({1'b0, n1OOi, n01ii, n01ll}),
	.o(wire_niO1l_o),
	.sel({n10OO, n1i1i}));
	defparam
		niO1l.width_data = 4,
		niO1l.width_sel = 2;
	oper_mux   niO1O
	( 
	.data({1'b0, n1OOl, n01il, n01lO}),
	.o(wire_niO1O_o),
	.sel({n10OO, n1i1i}));
	defparam
		niO1O.width_data = 4,
		niO1O.width_sel = 2;
	oper_mux   nllOi
	( 
	.data({wire_nlOOO_o, wire_nlOOl_o, wire_nlOOi_o, wire_nlOlO_o}),
	.o(wire_nllOi_o),
	.sel({wire_nlOll_o[2:1]}));
	defparam
		nllOi.width_data = 4,
		nllOi.width_sel = 2;
	oper_mux   nllOl
	( 
	.data({wire_n11i_o, wire_nlOOO_o, wire_nlOOl_o, wire_nlOOi_o}),
	.o(wire_nllOl_o),
	.sel({wire_nlOll_o[2:1]}));
	defparam
		nllOl.width_data = 4,
		nllOl.width_sel = 2;
	oper_mux   nllOO
	( 
	.data({wire_n11l_o, wire_n11i_o, wire_nlOOO_o, wire_nlOOl_o}),
	.o(wire_nllOO_o),
	.sel({wire_nlOll_o[2:1]}));
	defparam
		nllOO.width_data = 4,
		nllOO.width_sel = 2;
	oper_mux   nlO0i
	( 
	.data({wire_n10O_o, wire_n10l_o, wire_n10i_o, wire_n11O_o}),
	.o(wire_nlO0i_o),
	.sel({wire_nlOll_o[2:1]}));
	defparam
		nlO0i.width_data = 4,
		nlO0i.width_sel = 2;
	oper_mux   nlO0l
	( 
	.data({wire_n1ii_o, wire_n10O_o, wire_n10l_o, wire_n10i_o}),
	.o(wire_nlO0l_o),
	.sel({wire_nlOll_o[2:1]}));
	defparam
		nlO0l.width_data = 4,
		nlO0l.width_sel = 2;
	oper_mux   nlO0O
	( 
	.data({wire_n1il_o, wire_n1ii_o, wire_n10O_o, wire_n10l_o}),
	.o(wire_nlO0O_o),
	.sel({wire_nlOll_o[2:1]}));
	defparam
		nlO0O.width_data = 4,
		nlO0O.width_sel = 2;
	oper_mux   nlO1i
	( 
	.data({wire_n11O_o, wire_n11l_o, wire_n11i_o, wire_nlOOO_o}),
	.o(wire_nlO1i_o),
	.sel({wire_nlOll_o[2:1]}));
	defparam
		nlO1i.width_data = 4,
		nlO1i.width_sel = 2;
	oper_mux   nlO1l
	( 
	.data({wire_n10i_o, wire_n11O_o, wire_n11l_o, wire_n11i_o}),
	.o(wire_nlO1l_o),
	.sel({wire_nlOll_o[2:1]}));
	defparam
		nlO1l.width_data = 4,
		nlO1l.width_sel = 2;
	oper_mux   nlO1O
	( 
	.data({wire_n10l_o, wire_n10i_o, wire_n11O_o, wire_n11l_o}),
	.o(wire_nlO1O_o),
	.sel({wire_nlOll_o[2:1]}));
	defparam
		nlO1O.width_data = 4,
		nlO1O.width_sel = 2;
	oper_mux   nlOii
	( 
	.data({wire_n1iO_o, wire_n1il_o, wire_n1ii_o, wire_n10O_o}),
	.o(wire_nlOii_o),
	.sel({wire_nlOll_o[2:1]}));
	defparam
		nlOii.width_data = 4,
		nlOii.width_sel = 2;
	oper_mux   nlOil
	( 
	.data({wire_n1li_o[13], wire_n1iO_o, wire_n1il_o, wire_n1ii_o}),
	.o(wire_nlOil_o),
	.sel({wire_nlOll_o[2:1]}));
	defparam
		nlOil.width_data = 4,
		nlOil.width_sel = 2;
	oper_mux   nlOiO
	( 
	.data({{2{wire_n1li_o[13]}}, wire_n1iO_o, wire_n1il_o}),
	.o(wire_nlOiO_o),
	.sel({wire_nlOll_o[2:1]}));
	defparam
		nlOiO.width_data = 4,
		nlOiO.width_sel = 2;
	oper_mux   nlOli
	( 
	.data({{3{wire_n1li_o[13]}}, wire_n1iO_o}),
	.o(wire_nlOli_o),
	.sel({wire_nlOll_o[2:1]}));
	defparam
		nlOli.width_data = 4,
		nlOli.width_sel = 2;
	oper_mux   nlOlO
	( 
	.data({wire_n1li_o[12], wire_n1li_o[8], wire_n1li_o[4], wire_n1li_o[0]}),
	.o(wire_nlOlO_o),
	.sel({wire_nlOll_o[4:3]}));
	defparam
		nlOlO.width_data = 4,
		nlOlO.width_sel = 2;
	oper_mux   nlOOi
	( 
	.data({wire_n1li_o[13], wire_n1li_o[9], wire_n1li_o[5], wire_n1li_o[1]}),
	.o(wire_nlOOi_o),
	.sel({wire_nlOll_o[4:3]}));
	defparam
		nlOOi.width_data = 4,
		nlOOi.width_sel = 2;
	oper_mux   nlOOl
	( 
	.data({wire_n1li_o[13], wire_n1li_o[10], wire_n1li_o[6], wire_n1li_o[2]}),
	.o(wire_nlOOl_o),
	.sel({wire_nlOll_o[4:3]}));
	defparam
		nlOOl.width_data = 4,
		nlOOl.width_sel = 2;
	oper_mux   nlOOO
	( 
	.data({wire_n1li_o[13], wire_n1li_o[11], wire_n1li_o[7], wire_n1li_o[3]}),
	.o(wire_nlOOO_o),
	.sel({wire_nlOll_o[4:3]}));
	defparam
		nlOOO.width_data = 4,
		nlOOO.width_sel = 2;
	assign
		nlOliO = ((((((((((~ n100i) & (~ n101O)) & (~ n101l)) & (~ n101i)) & (~ n11OO)) & (~ n11Ol)) & (~ n11Oi)) & (~ n11lO)) & (~ n11ll)) & (~ n11li)),
		nlOlli = ((((((((((~ wire_nil_dataout) & (~ wire_nii_dataout)) & (~ wire_n0O_dataout)) & (~ wire_n0l_dataout)) & (~ wire_n0i_dataout)) & (~ wire_n1O_dataout)) & (~ wire_n1l_dataout)) & (~ wire_n1i_dataout)) & (~ wire_nlOO_dataout)) & (~ wire_nlOl_dataout)),
		nlOlll = ((((n110i & n111O) & n111l) & n111i) & nlOOOO),
		nlOllO = (((wire_nl01O_dataout & nlOOii) & n10OO) & n1i1i),
		nlOlOi = (((((((~ n0i1i) & (~ n00OO)) & n00Ol) & n00Oi) & n00lO) & n00ll) & n00li),
		nlOlOl = (nlOO0O & nlOO1O),
		nlOlOO = ((n1O0l | n1O0O) | ((n1Oli & n1Oll) & n1Oii)),
		nlOO0i = (((((~ n1l0i) & (~ n1l1O)) & (~ n1l1l)) & (~ n1l1i)) & (~ n1iOO)),
		nlOO0l = ((((n1l0i & n1l1O) & n1l1l) & n1l1i) & n1iOO),
		nlOO0O = ((~ n1ilO) & n1iOi),
		nlOO1i = (nlOO0l & n1O1O),
		nlOO1l = (n1ilO & n1O1i),
		nlOO1O = ((~ nlOO0l) & (~ nlOO0i)),
		nlOOii = ((~ wire_nl00O_dataout) & (~ wire_nl00l_dataout)),
		nlOOil = ((((((((~ wire_nl0Ol_o[6]) & (~ wire_nl0Ol_o[7])) & (~ wire_nl0Ol_o[8])) & (~ wire_nl0Ol_o[9])) & (~ wire_nl0Ol_o[10])) & (~ wire_nl0Ol_o[11])) & (~ wire_nl0Ol_o[12])) & (~ wire_nl0Ol_o[13])),
		nlOOiO = 1'b1,
		nlOOli = (((((~ wire_ni_dataout) & (~ wire_nlO_dataout)) & (~ wire_nll_dataout)) & (~ wire_nli_dataout)) & (~ wire_niO_dataout)),
		q = {((~ nlOlOO) & n1O0i), wire_nii0i_o, wire_nii1O_o, wire_nii1l_o, wire_nii1i_o, wire_ni0OO_o, wire_ni0Ol_o, wire_ni0Oi_o, wire_ni0lO_o, wire_ni0ll_o, wire_ni0li_o, wire_ni0iO_o, wire_ni0il_o, wire_ni0ii_o, wire_ni00O_o, wire_ni00l_o};
endmodule //ip_fp_add
//synopsys translate_on
//VALID FILE