1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
|
.section .interrupt_vector
__reset:
b _start
__undefined:
b undefined
__swi:
b swi
__prefetch_abort:
b prefetch_abort
__data_abort:
b data_abort
__reserved:
b .
__irq:
b irq
__fiq:
b .
.text
.global _start
_start:
ldr r0, =_boot_num
ldr r1, [r0]
add r2, r1, #1
str r2, [r0]
ldr r2, =__cpus
lsl r3, r1, #2
ldr ip, [r2, r3]
str r1, [ip]
ldr r2, =_stack_shift
lsl r1, r1, r2
ldr sp, =_stack_begin
add sp, sp, r1
mov lr, #0
bl reset
b .
_boot_num:
.word 0
irq:
subs pc, lr, #4
.weak undefined, swi, data_abort, prefetch_abort, irq
.set swi, __swi
.set undefined, __undefined
.set data_abort, __data_abort
.set prefetch_abort, __prefetch_abort
|
