| Age | Commit message (Expand) | Author |
|---|---|---|
| 2022-10-17 | Break false dependency on r0 for MOV/MVN | Alejandro Soto |
| 2022-10-17 | Improve sim.py output | Alejandro Soto |
| 2022-10-16 | Implement register dumps | Alejandro Soto |
| 2022-10-16 | Add C simulation testbench | Alejandro Soto |
| 2022-10-16 | Add original simulation testbench | Alejandro Soto |
| 2022-10-16 | Implement simulation testbenches | Alejandro Soto |
| 2022-10-15 | Rework bus architecture | Alejandro Soto |
| 2022-09-27 | Add simple loop execution testbench | Alejandro Soto |
| 2022-09-25 | Rename HPS SDRAM testbench file | Alejandro Soto |
| 2022-09-18 | Rename data_rw to data_wr in bus master | Alejandro Soto |
| 2022-09-18 | Fix public_flat_rw signals | Alejandro Soto |
| 2022-09-18 | Fix memory simulation | Alejandro Soto |
| 2022-09-18 | Implement Avalon memory module for simulation | Alejandro Soto |
| 2022-09-18 | Update testbench | Alejandro Soto |
| 2022-09-18 | Add Avalon-MM emulator | Alejandro Soto |
| 2022-09-17 | Update project structure to match Verilator Makefile | Alejandro Soto |
| 2022-09-01 | Initial commit | Alejandro Soto |
 |
index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
| summaryrefslogtreecommitdiff |