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Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.
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2023-09-24
tb: implement support for cache line-sized slaves
Alejandro Soto
2022-12-21
Fix clock/reset timing in single-step, dsp_mul
Alejandro Soto
2022-12-18
Implement privileged ldm/stm of user registers
Alejandro Soto
2022-12-18
Fix datapath of shifter carry-out during adc/sbc/rsc
Alejandro Soto
2022-12-16
Improve simulation performance for the most common case
Alejandro Soto
2022-12-16
Implement swi (system call)
Alejandro Soto
2022-12-16
Implement branch history (simulation only)
Alejandro Soto
2022-12-16
Fix register corruption when interrupting a load-store
Alejandro Soto
2022-12-16
Fix implementation of MMU access faults
Alejandro Soto
2022-12-16
Implement interrupt emulation
Alejandro Soto
2022-12-16
Implement interrupt controller
Alejandro Soto
2022-12-16
Implement fast video
Alejandro Soto
2022-12-16
Fix sysctrl register dump
Alejandro Soto
2022-12-16
Implement page walks in patch-mem
Alejandro Soto
2022-12-16
Implement gdbstub monitor
Alejandro Soto
2022-12-16
Show main cp15 registers in register dumps
Alejandro Soto
2022-12-16
Implement prefetch aborts
Alejandro Soto
2022-12-16
Implement register writes from gdb
Alejandro Soto
2022-12-16
Implement MMU access checks
Alejandro Soto
2022-12-16
Implement data aborts
Alejandro Soto
2022-12-16
Implement hardware virtual memory
Alejandro Soto
2022-12-09
Implement CP15 ID register
Alejandro Soto
2022-12-09
Implement cp15 control
Alejandro Soto
2022-12-08
Fix decoding of msr with immediate operand
Alejandro Soto
2022-12-08
Support gdb interrupts
Alejandro Soto
2022-12-07
Fix register-indirect shifts
Alejandro Soto
2022-12-07
Make the cycle limit optional
Alejandro Soto
2022-12-07
Implement single-stepping
Alejandro Soto
2022-12-06
Implement breakpoints
Alejandro Soto
2022-12-06
Implement gdbstub
Alejandro Soto
2022-11-20
Add tick, bail signals to simulated Avalon slaves
Alejandro Soto
2022-11-19
Implement JTAG-UART input
Alejandro Soto
2022-11-19
Implement interval timer simulation
Alejandro Soto
2022-11-17
Finish simulation
Alejandro Soto
2022-11-17
Fix sim
Alejandro Soto
2022-11-17
Implement sim test: descifrador
Alejandro Soto
2022-11-17
Bug fixes
JulianCamacho
2022-11-16
Gracefully exit when Avalon assertions fail during simulation
Alejandro Soto
2022-11-16
Implement JTAG-UART tx emulation
Alejandro Soto
2022-11-16
Implement bx lr
Alejandro Soto
2022-11-16
Implement privilege escalation
Alejandro Soto
2022-11-16
Implement psr read/write logic
Alejandro Soto
2022-11-16
Add sim test: subword
Alejandro Soto
2022-11-15
Implemente byte-enable signal in stores
Alejandro Soto
2022-11-15
Replace vga_controller with streaming Altera IP
Alejandro Soto
2022-11-14
Implement VGA simulation
Alejandro Soto
2022-11-13
Implement CPU halt
Alejandro Soto
2022-11-13
Route cpu_rst_n signal through bus master
Alejandro Soto
2022-11-13
Add reset debounce
Alejandro Soto
2022-11-13
Hardwire PLL reset to ground
Alejandro Soto
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