| Age | Commit message (Expand) | Author |
|---|---|---|
| 2022-11-09 | Implement initial state randomization in sim | Alejandro Soto |
| 2022-11-09 | Update fetch, decode testbenches | Alejandro Soto |
| 2022-11-07 | Añade testbench para fetch y decode | JulianCamacho |
| 2022-11-07 | Adding decode instructions for test | JulianCamacho |
| 2022-11-07 | Adding decode test | JulianCamacho |
| 2022-11-06 | Export PSRs to simulation | Alejandro Soto |
| 2022-10-30 | Se agregan test de mul | JulianCamacho |
| 2022-10-18 | Support program counter in --dump-regs | Alejandro Soto |
| 2022-10-18 | Implement register initialization in sim | Alejandro Soto |
| 2022-10-16 | Implement register dumps | Alejandro Soto |
| 2022-10-16 | Implement simulation testbenches | Alejandro Soto |
| 2022-09-27 | Add simple loop execution testbench | Alejandro Soto |
| 2022-09-25 | Rename HPS SDRAM testbench file | Alejandro Soto |
| 2022-09-18 | Fix memory simulation | Alejandro Soto |
| 2022-09-18 | Update testbench | Alejandro Soto |
| 2022-09-17 | Update project structure to match Verilator Makefile | Alejandro Soto |
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index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
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