conspiracion - Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.

Age	Commit message (Expand)	Author
2023-10-04	rtl/cache: increase to 64KiB per core	Alejandro Soto
2023-10-04	demo: implement cache debug	Alejandro Soto
2023-10-04	rtl/cache: implement debug interface	Alejandro Soto
2023-10-03	tb: fix halt force	Alejandro Soto
2023-10-02	tb: implement verilated slaves	Alejandro Soto
2023-10-01	tb: implement quad-core SMP	Alejandro Soto
2023-09-29	tb: enable sim performance flags ("faster is better")	Alejandro Soto
2023-09-25	tb: implement coverage reports	Alejandro Soto
2023-09-25	rtl/core, tb: replace bus_master with a new top-level module	Alejandro Soto
2023-09-25	tb: implement cache ring	Alejandro Soto
2023-09-24	tb: implement support for cache line-sized slaves	Alejandro Soto
2022-12-16	Improve simulation performance for the most common case	Alejandro Soto
2022-12-16	Implement branch history (simulation only)	Alejandro Soto
2022-12-16	Fix implementation of MMU access faults	Alejandro Soto
2022-12-16	Implement interrupt controller	Alejandro Soto
2022-12-16	Implement fast video	Alejandro Soto
2022-12-16	Fix sysctrl register dump	Alejandro Soto
2022-12-16	Implement page walks in patch-mem	Alejandro Soto
2022-12-16	Implement gdbstub monitor	Alejandro Soto
2022-12-16	Show main cp15 registers in register dumps	Alejandro Soto
2022-12-16	Implement register writes from gdb	Alejandro Soto
2022-12-16	Implement hardware virtual memory	Alejandro Soto
2022-12-08	Support gdb interrupts	Alejandro Soto
2022-12-07	Make the cycle limit optional	Alejandro Soto
2022-12-07	Implement single-stepping	Alejandro Soto
2022-12-06	Implement breakpoints	Alejandro Soto
2022-12-06	Implement gdbstub	Alejandro Soto
2022-11-20	Add tick, bail signals to simulated Avalon slaves	Alejandro Soto
2022-11-19	Implement JTAG-UART input	Alejandro Soto
2022-11-19	Implement interval timer simulation	Alejandro Soto
2022-11-17	Finish simulation	Alejandro Soto
2022-11-17	Implement sim test: descifrador	Alejandro Soto
2022-11-16	Gracefully exit when Avalon assertions fail during simulation	Alejandro Soto
2022-11-16	Implement JTAG-UART tx emulation	Alejandro Soto
2022-11-14	Implement VGA simulation	Alejandro Soto
2022-11-13	Implement CPU halt	Alejandro Soto
2022-11-13	Add reset debounce	Alejandro Soto
2022-11-09	Implement initial state randomization in sim	Alejandro Soto
2022-11-09	Update fetch, decode testbenches	Alejandro Soto
2022-11-07	Añade testbench para fetch y decode	JulianCamacho
2022-11-07	Adding decode instructions for test	JulianCamacho
2022-11-07	Adding decode test	JulianCamacho
2022-11-06	Export PSRs to simulation	Alejandro Soto
2022-10-30	Se agregan test de mul	JulianCamacho
2022-10-18	Support program counter in --dump-regs	Alejandro Soto
2022-10-18	Implement register initialization in sim	Alejandro Soto
2022-10-16	Implement register dumps	Alejandro Soto
2022-10-16	Implement simulation testbenches	Alejandro Soto
2022-09-27	Add simple loop execution testbench	Alejandro Soto
2022-09-25	Rename HPS SDRAM testbench file	Alejandro Soto