| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2022-11-07 | Add test sim: modeswitch | Alejandro Soto | |
| 2022-11-07 | Improve mult sim | Alejandro Soto | |
| 2022-10-31 | Show simulator output in sim testbenches | Alejandro Soto | |
| 2022-10-25 | Implement explicit sim state dump | Alejandro Soto | |
| 2022-10-25 | Add sim test: tarea2 | Alejandro Soto | |
| 2022-10-23 | Add sim test: shifts | Alejandro Soto | |
| 2022-10-23 | Add sim test: stack | Alejandro Soto | |
| 2022-10-18 | Add sim test: control_flow | Alejandro Soto | |
| 2022-10-18 | Add sim test: mult | Alejandro Soto | |
| 2022-10-18 | Print simulator command line on test failure | Alejandro Soto | |
| 2022-10-18 | Support skipping tests | Alejandro Soto | |
| 2022-10-18 | Implement register initialization in sim | Alejandro Soto | |
| 2022-10-17 | Break false dependency on r0 for MOV/MVN | Alejandro Soto | |
| 2022-10-17 | Improve sim.py output | Alejandro Soto | |
| 2022-10-16 | Implement register dumps | Alejandro Soto | |
| 2022-10-16 | Add C simulation testbench | Alejandro Soto | |
| 2022-10-16 | Add original simulation testbench | Alejandro Soto | |
| 2022-10-16 | Implement simulation testbenches | Alejandro Soto | |
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index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
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