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AgeCommit message (Collapse)Author
2022-11-09Implement initial state randomization in simAlejandro Soto
2022-11-09Fix bus protocol errors in bus masterAlejandro Soto
2022-11-08Fix handling of multi-cycle Avalon waitrequest states in bus masterAlejandro Soto
2022-11-08Add sim: sdramAlejandro Soto
2022-11-07Add test sim: modeswitchAlejandro Soto
2022-11-07Improve mult simAlejandro Soto
2022-10-31Show simulator output in sim testbenchesAlejandro Soto
2022-10-25Implement explicit sim state dumpAlejandro Soto
2022-10-25Add sim test: tarea2Alejandro Soto
2022-10-23Add sim test: shiftsAlejandro Soto
2022-10-23Add sim test: stackAlejandro Soto
2022-10-18Add sim test: control_flowAlejandro Soto
2022-10-18Add sim test: multAlejandro Soto
2022-10-18Print simulator command line on test failureAlejandro Soto
2022-10-18Support skipping testsAlejandro Soto
2022-10-18Implement register initialization in simAlejandro Soto
2022-10-17Break false dependency on r0 for MOV/MVNAlejandro Soto
2022-10-17Improve sim.py outputAlejandro Soto
2022-10-16Implement register dumpsAlejandro Soto
2022-10-16Add C simulation testbenchAlejandro Soto
2022-10-16Add original simulation testbenchAlejandro Soto
2022-10-16Implement simulation testbenchesAlejandro Soto
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