| Age | Commit message (Expand) | Author |
|---|---|---|
| 2024-02-20 | tb/sim: update constant in hazards test | Alejandro Soto |
| 2022-11-09 | Fix bus protocol errors in bus master | Alejandro Soto |
| 2022-10-16 | Implement register dumps | Alejandro Soto |
| 2022-10-16 | Add original simulation testbench | Alejandro Soto |
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index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
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