| Age | Commit message (Expand) | Author |
|---|---|---|
| 2023-09-24 | tb: implement support for cache line-sized slaves | Alejandro Soto |
| 2022-11-14 | Implement VGA simulation | Alejandro Soto |
| 2022-11-08 | Fix handling of multi-cycle Avalon waitrequest states in bus master | Alejandro Soto |
| 2022-10-16 | Implement simulation testbenches | Alejandro Soto |
| 2022-09-27 | Add simple loop execution testbench | Alejandro Soto |
| 2022-09-18 | Implement Avalon memory module for simulation | Alejandro Soto |
 |
index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
| summaryrefslogtreecommitdiff |