| Age | Commit message (Expand) | Author |
|---|---|---|
| 2022-12-16 | Implement hardware virtual memory | Alejandro Soto |
| 2022-12-06 | Implement gdbstub | Alejandro Soto |
| 2022-11-20 | Add tick, bail signals to simulated Avalon slaves | Alejandro Soto |
| 2022-11-16 | Gracefully exit when Avalon assertions fail during simulation | Alejandro Soto |
| 2022-11-14 | Implement VGA simulation | Alejandro Soto |
| 2022-11-09 | Implement initial state randomization in sim | Alejandro Soto |
| 2022-10-16 | Implement simulation testbenches | Alejandro Soto |
| 2022-10-15 | Rework bus architecture | Alejandro Soto |
| 2022-09-18 | Fix memory simulation | Alejandro Soto |
| 2022-09-18 | Add Avalon-MM emulator | Alejandro Soto |
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index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
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