conspiracion - Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.

Age	Commit message (Expand)	Author
2024-05-05	rtl/legacy_gfx: rename gfx -> legacy_gfx	Alejandro Soto
2024-04-27	target/de1soc: move quartus files out of project root	Alejandro Soto
2024-02-20	mk: implement support for quartus synthesis	Alejandro Soto
2024-02-20	rtl, tb: add core.mk files	Alejandro Soto
2023-11-20	rtl/gfx: implement host memory interface	Alejandro Soto
2023-11-19	rtl/gfx: fix mem_address units to bytes instead of words	Alejandro Soto
2023-11-17	tb: add test: fifo	Alejandro Soto
2023-11-16	rtl/smp: implement SMP dead/alive handling	Alejandro Soto
2023-10-29	rtl/gfx: implement double-buffered scanout	Alejandro Soto
2023-10-28	tb: add block test: test_fb	Alejandro Soto
2023-10-06	tb: implement ring test	Alejandro Soto
2023-10-06	tb: rename smp_sim to test_smp	Alejandro Soto
2023-10-05	tb: implement block test: smp_sim reset	Alejandro Soto
2023-10-05	Makefile, tb: add support for cocotb	Alejandro Soto
2023-09-30	platform: implement SMP controller	Alejandro Soto
2023-09-25	rtl/core, tb: replace bus_master with a new top-level module	Alejandro Soto
2022-12-21	Fix clock/reset timing in single-step, dsp_mul	Alejandro Soto
2022-12-07	Implement single-stepping	Alejandro Soto
2022-12-06	Implement breakpoints	Alejandro Soto
2022-12-06	Implement gdbstub	Alejandro Soto
2022-11-17	Bug fixes	JulianCamacho
2022-11-15	Implemente byte-enable signal in stores	Alejandro Soto
2022-11-15	Replace vga_controller with streaming Altera IP	Alejandro Soto
2022-11-14	Fix VRAM clock	Alejandro Soto
2022-11-13	Restore clock connections in Platform Designer	Alejandro Soto
2022-11-13	Implement CPU halt	Alejandro Soto
2022-11-13	Route cpu_rst_n signal through bus master	Alejandro Soto
2022-11-13	Add reset debounce	Alejandro Soto
2022-11-13	Hardwire PLL reset to ground	Alejandro Soto
2022-11-09	Implement reset	Alejandro Soto
2022-11-09	Update fetch, decode testbenches	Alejandro Soto
2022-11-08	Add missing toplevel pin connections	Alejandro Soto
2022-11-07	Añade testbench para fetch y decode	JulianCamacho
2022-11-07	Adding decode test	JulianCamacho
2022-11-03	Add toplevel wires for VGA DAC	Alejandro Soto
2022-11-02	Use PLL output as CPU clock	Alejandro Soto
2022-11-02	Add bus master forward signals: irq, cpu_clk	Alejandro Soto
2022-11-02	Add new toplevel signals	Alejandro Soto
2022-10-30	Se agregan test de mul	JulianCamacho
2022-10-02	Use @(posedge clk) in register files	Alejandro Soto
2022-09-27	Add simple loop execution testbench	Alejandro Soto
2022-09-23	Add toplevel module for core tests	Alejandro Soto
2022-09-23	Rename conspiracion.sv test as hps_sdram_test.sv	Alejandro Soto
2022-09-19	DDR3 is working	Alejandro Soto
2022-09-18	Rename data_rw to data_wr in bus master	Alejandro Soto
2022-09-18	Update testbench	Alejandro Soto
2022-09-17	Update project structure to match Verilator Makefile	Alejandro Soto