conspiracion - Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.

Age	Commit message (Expand)	Author
2022-11-14	Fix VRAM clock	Alejandro Soto
2022-11-13	Restore clock connections in Platform Designer	Alejandro Soto
2022-11-13	Implement CPU halt	Alejandro Soto
2022-11-13	Route cpu_rst_n signal through bus master	Alejandro Soto
2022-11-13	Add reset debounce	Alejandro Soto
2022-11-13	Hardwire PLL reset to ground	Alejandro Soto
2022-11-09	Implement reset	Alejandro Soto
2022-11-09	Update fetch, decode testbenches	Alejandro Soto
2022-11-08	Add missing toplevel pin connections	Alejandro Soto
2022-11-07	Añade testbench para fetch y decode	JulianCamacho
2022-11-07	Adding decode test	JulianCamacho
2022-11-03	Add toplevel wires for VGA DAC	Alejandro Soto
2022-11-02	Use PLL output as CPU clock	Alejandro Soto
2022-11-02	Add bus master forward signals: irq, cpu_clk	Alejandro Soto
2022-11-02	Add new toplevel signals	Alejandro Soto
2022-10-30	Se agregan test de mul	JulianCamacho
2022-10-02	Use @(posedge clk) in register files	Alejandro Soto
2022-09-27	Add simple loop execution testbench	Alejandro Soto
2022-09-23	Add toplevel module for core tests	Alejandro Soto
2022-09-23	Rename conspiracion.sv test as hps_sdram_test.sv	Alejandro Soto
2022-09-19	DDR3 is working	Alejandro Soto
2022-09-18	Rename data_rw to data_wr in bus master	Alejandro Soto
2022-09-18	Update testbench	Alejandro Soto
2022-09-17	Update project structure to match Verilator Makefile	Alejandro Soto