| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2023-11-02 | ip: add ip_fp_inv | Alejandro Soto | |
| 2023-10-29 | rtl/gfx: implement scanout command interface | Alejandro Soto | |
| 2023-10-29 | rtl/gfx: implement double-buffered scanout | Alejandro Soto | |
| 2023-10-28 | rtl/gfx: add debug registers | Alejandro Soto | |
| 2023-10-27 | rtl/gfx: implement fp16 on verilator | Alejandro Soto | |
| 2023-10-27 | rtl/gfx: fix linear combiner | Alejandro Soto | |
| 2023-10-26 | rtl/gfx: implement matrix transpose | Alejandro Soto | |
| 2023-10-26 | rtl/gfx: fix deadlock in fold_flow | Alejandro Soto | |
| 2023-10-26 | rtl/gfx: synchronize clock with SDRAM | Alejandro Soto | |
| 2023-10-25 | platform: add mem master to gfx | Alejandro Soto | |
| 2023-10-25 | rtl/gfx: implement skid buffers | Alejandro Soto | |
| 2023-10-22 | rtl/gfx: reimplement multiplier as a much smaller mat-vec pipeline | Alejandro Soto | |
| 2023-10-21 | ip: downgrade to 16-bit floats | Alejandro Soto | |
| 2023-10-21 | rtl/gfx: implement non-synthesizable matrix multiplier | Alejandro Soto | |
 |
index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
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