| Age | Commit message (Expand) | Author |
|---|---|---|
| 2023-10-27 | rtl/gfx: implement fp16 on verilator | Alejandro Soto |
| 2023-10-22 | rtl/gfx: reimplement multiplier as a much smaller mat-vec pipeline | Alejandro Soto |
| 2023-10-21 | ip: downgrade to 16-bit floats | Alejandro Soto |
| 2023-10-21 | rtl/gfx: implement non-synthesizable matrix multiplier | Alejandro Soto |
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index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
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