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Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.
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2022-09-25
Shorten decode_* nets to dec_*
Alejandro Soto
2022-09-25
Implement flag updates
Alejandro Soto
2022-09-25
Refactor CPSR and uarch.sv
Alejandro Soto
2022-09-25
Fix Quartus issues
Alejandro Soto
2022-09-25
Implement PSR flag handling
Alejandro Soto
2022-09-25
Implement ALU opcode decoding
Alejandro Soto
2022-09-25
Implement ALU
Alejandro Soto
2022-09-25
Implement initial cycle control logic
Alejandro Soto
2022-09-25
Add fetch jump target
Alejandro Soto
2022-09-25
Fetch NOP on prefetch flush
Alejandro Soto
2022-09-25
Implement branch handling in decode
Alejandro Soto
2022-09-25
Use word/ptr instead of logic[..]
Alejandro Soto
2022-09-25
Implement register file
Alejandro Soto
2022-09-24
Implement initial decoder
Alejandro Soto
2022-09-24
Implement decode of branch instructions
Alejandro Soto
2022-09-24
Implement decode of ALU instructions
Alejandro Soto
2022-09-24
Add instruction encodings
Alejandro Soto
2022-09-23
Add toplevel module for core tests
Alejandro Soto
2022-09-23
Implement core stub
Alejandro Soto
2022-09-23
Implement initial fetch stage
Alejandro Soto