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Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.
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psr.sv
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2022-12-16
Fix privilege escalation while in user mode
Alejandro Soto
2022-12-16
Implement mode privilege checks in MMU
Alejandro Soto
2022-11-16
Implement psr read/write logic
Alejandro Soto
2022-11-16
Simplify flags datapath
Alejandro Soto
2022-11-16
Finish decode of psr operations
Alejandro Soto
2022-11-09
Implement reset
Alejandro Soto
2022-11-07
Quartus has not support for unique0
Alejandro Soto
2022-11-06
Export PSRs to simulation
Alejandro Soto
2022-11-06
Implement PSR modes and interrupt masks
Alejandro Soto
2022-10-09
Pipeline flags writeback (breaks combinational data dependencies)
Alejandro Soto
2022-10-03
Fix pipeline hazards
Alejandro Soto
2022-10-02
Major shifter-ALU redesign
Alejandro Soto
2022-09-27
Switch from operand forwarding to next insn stalls (improves Fmax)
Alejandro Soto
2022-09-25
Implement flag updates
Alejandro Soto
2022-09-25
Refactor CPSR and uarch.sv
Alejandro Soto
2022-09-25
Implement register file
Alejandro Soto
2022-09-24
Implement decode of ALU instructions
Alejandro Soto