| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2022-09-25 | Implement shifter decoding | Alejandro Soto | |
| 2022-09-25 | Refactor CPSR and uarch.sv | Alejandro Soto | |
| 2022-09-25 | Implement ALU | Alejandro Soto | |
| 2022-09-25 | Implement register file | Alejandro Soto | |
| 2022-09-24 | Implement decode of ALU instructions | Alejandro Soto | |
| 2022-09-24 | Add instruction encodings | Alejandro Soto | |
 |
index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
| summaryrefslogtreecommitdiff |