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authorAlejandro Soto <alejandro@34project.org>2022-09-25 19:55:29 -0600
committerAlejandro Soto <alejandro@34project.org>2022-09-25 19:55:29 -0600
commitfa370016708149976c748c14eadad1f89cf5a8ea (patch)
tree785ca92bebaef645e15f26a97d4892ef2ba2dad9 /rtl/core/isa.sv
parent3aa075cf009d9aa8c602389853cc3ea78cda8701 (diff)
Refactor CPSR and uarch.sv
Diffstat (limited to 'rtl/core/isa.sv')
-rw-r--r--rtl/core/isa.sv5
1 files changed, 0 insertions, 5 deletions
diff --git a/rtl/core/isa.sv b/rtl/core/isa.sv
index 710b11b..1778d33 100644
--- a/rtl/core/isa.sv
+++ b/rtl/core/isa.sv
@@ -4,11 +4,6 @@
`define FIELD_COND [31:28]
`define FIELD_OP [27:0]
-typedef logic[3:0] reg_num;
-
-`define R14 4'b1110
-`define R15 4'b1111
-
`define COND_EQ 4'b0000
`define COND_NE 4'b0001
`define COND_HS 4'b0010