| Age | Commit message (Expand) | Author |
|---|---|---|
| 2023-10-02 | rtl/core: implement ldrex/strex decode | Alejandro Soto |
| 2022-12-16 | Implement swi (system call) | Alejandro Soto |
| 2022-12-07 | Implement single-stepping | Alejandro Soto |
| 2022-12-06 | Implement breakpoints | Alejandro Soto |
| 2022-11-16 | Implement bx lr | Alejandro Soto |
| 2022-11-16 | Implement psr read/write logic | Alejandro Soto |
| 2022-11-16 | Finish decode of psr operations | Alejandro Soto |
| 2022-11-16 | Fix decoding of LDST_MISC group | Alejandro Soto |
| 2022-11-10 | Fix reset glitches | Alejandro Soto |
| 2022-11-08 | Register decode output in a new porch stage | Alejandro Soto |
| 2022-11-08 | Rename datapath_decode as ctrl_decode | Alejandro Soto |
| 2022-11-07 | Fix flags hazard in ADC, SBC, RSC | Alejandro Soto |
| 2022-11-07 | Quartus has not support for unique0 | Alejandro Soto |
| 2022-11-07 | Implement multiplication control | Alejandro Soto |
| 2022-11-07 | Split decode mux logic out of decode.sv | Alejandro Soto |
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index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
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