| Age | Commit message (Expand) | Author |
|---|---|---|
| 2024-02-20 | rtl: refactor filenames and directory hierarchy | Alejandro Soto |
| 2023-10-02 | rtl/core: implement ldrex/strex decode | Alejandro Soto |
| 2022-11-01 | Replace decode enable signals with datapath signals | Alejandro Soto |
| 2022-10-17 | Fix unsafe decode signals | Alejandro Soto |
| 2022-10-16 | Move isa.sv to core/decode | Alejandro Soto |
| 2022-10-09 | Implement most memory transactions | Alejandro Soto |
| 2022-10-08 | Implement LDR/STR decode | Alejandro Soto |
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index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
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