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Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.
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rtl
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core
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decode
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decode.sv
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Author
2022-10-23
Pack general control signals as struct datapath_decode
Alejandro Soto
2022-10-23
Move signal `uses_rn` to struct data_decode
Alejandro Soto
2022-10-23
Move branch control signals to struct branch_decode
Alejandro Soto
2022-10-18
Implement branch with link
Alejandro Soto
2022-10-18
Implement undefined instruction exceptions
Alejandro Soto
2022-10-17
Break false dependency on r0 for MOV/MVN
Alejandro Soto
2022-10-17
Fix unsafe decode signals
Alejandro Soto
2022-10-16
Move isa.sv to core/decode
Alejandro Soto
2022-10-15
Fix flags and writeback hazards
Alejandro Soto
2022-10-09
Implement most memory transactions
Alejandro Soto
2022-10-08
Implement LDR/STR decode
Alejandro Soto
2022-10-02
Split decoding of flexible second operand out of data instructions
Alejandro Soto
2022-10-02
Major shifter-ALU redesign
Alejandro Soto
2022-09-27
Fix branching bugs
Alejandro Soto
2022-09-25
Implement shifter decoding
Alejandro Soto
2022-09-25
Implement flag updates
Alejandro Soto
2022-09-25
Refactor CPSR and uarch.sv
Alejandro Soto
2022-09-25
Fix Quartus issues
Alejandro Soto
2022-09-25
Implement ALU opcode decoding
Alejandro Soto
2022-09-25
Implement branch handling in decode
Alejandro Soto
2022-09-24
Implement initial decoder
Alejandro Soto