| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2022-12-18 | Implement privileged ldm/stm of user registers | Alejandro Soto | |
| 2022-12-07 | Fix register-indirect shifts | Alejandro Soto | |
| 2022-11-16 | Implement psr read/write logic | Alejandro Soto | |
| 2022-11-15 | Rewrite duplicate ldst logic as signal ldst_next | Alejandro Soto | |
| 2022-11-13 | Convert core state machines to Quartus-inferring RTL | Alejandro Soto | |
| 2022-11-09 | Implement reset | Alejandro Soto | |
| 2022-11-08 | Refactor decode signals into unified insn_decode struct | Alejandro Soto | |
| 2022-11-07 | Remove false dependencies on control.issue (long combinational) | Alejandro Soto | |
| 2022-11-07 | Rework regfile in order to remove negedge trigger | Alejandro Soto | |
| 2022-11-07 | Quartus has not support for unique0 | Alejandro Soto | |
| 2022-11-07 | Implement multiplication control | Alejandro Soto | |
| 2022-11-06 | Clean-up control.sv | Alejandro Soto | |
| 2022-11-06 | Split regfile read select logic out of control.sv | Alejandro Soto | |
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index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
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