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| author | Alejandro Soto <alejandro@34project.org> | 2022-11-08 00:19:49 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-11-08 00:19:49 -0600 |
| commit | ac0d6f4e068ff0ff08f05e04053ebd53ba20bcb8 (patch) | |
| tree | 8c2019cb296f94b2fd39894a245a4aac899d2371 /rtl/core/control/select.sv | |
| parent | 942461c315db3269fcbe9a9ca18beee9afa78d9c (diff) | |
Refactor decode signals into unified insn_decode struct
Diffstat (limited to 'rtl/core/control/select.sv')
| -rw-r--r-- | rtl/core/control/select.sv | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/rtl/core/control/select.sv b/rtl/core/control/select.sv index 62ad503..09fb144 100644 --- a/rtl/core/control/select.sv +++ b/rtl/core/control/select.sv @@ -4,8 +4,7 @@ module core_control_select ( input logic clk, - input data_decode dec_data, - input snd_decode dec_snd, + input insn_decode dec, input ctrl_cycle cycle, next_cycle, @@ -31,13 +30,13 @@ module core_control_select unique case(next_cycle) ISSUE: begin - ra = dec_data.rn; - rb = dec_snd.r; + ra = dec.data.rn; + rb = dec.snd.r; end TRANSFER: if(cycle != TRANSFER || mem_ready) - // final_rd viene de dec_ldst.rd + // final_rd viene de dec.ldst.rd rb = pop_valid ? popped : final_rd; MUL_ACC_LD: begin @@ -52,7 +51,7 @@ module core_control_select last_rb <= rb; if(next_cycle == ISSUE) - r_shift <= dec_snd.r_shift; + r_shift <= dec.snd.r_shift; end initial begin |