| Age | Commit message (Expand) | Author |
|---|---|---|
| 2023-09-25 | rtl/core, tb: replace bus_master with a new top-level module | Alejandro Soto |
| 2022-12-18 | Implement privileged ldm/stm of user registers | Alejandro Soto |
| 2022-12-16 | Fix register corruption when interrupting a load-store | Alejandro Soto |
| 2022-12-16 | Implement data aborts | Alejandro Soto |
| 2022-11-16 | Implement privilege escalation | Alejandro Soto |
| 2022-11-16 | Implement psr read/write logic | Alejandro Soto |
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index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
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