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Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.
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rtl
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control
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ldst
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2023-10-02
rtl/core/control: implement exclusive ldst
Alejandro Soto
2023-10-02
rtl: implement exclusive monitor datapath
Alejandro Soto
2022-12-18
Implement mode-translated memory accesses
Alejandro Soto
2022-12-16
Fix register corruption when interrupting a load-store
Alejandro Soto
2022-12-16
Implement data aborts
Alejandro Soto
2022-11-15
Implemente byte-enable signal in stores
Alejandro Soto
2022-11-15
Implement sub-word memory accesses
Alejandro Soto
2022-11-15
Rewrite duplicate ldst logic as signal ldst_next
Alejandro Soto
2022-11-13
Convert core state machines to Quartus-inferring RTL
Alejandro Soto
2022-11-10
Fix reset glitches
Alejandro Soto
2022-11-09
Implement reset
Alejandro Soto
2022-11-08
Refactor decode signals into unified insn_decode struct
Alejandro Soto
2022-11-07
Remove false dependencies on control.issue (long combinational)
Alejandro Soto
2022-11-07
Quartus has not support for unique0
Alejandro Soto
2022-11-06
Move load-store logic out of control.sv
Alejandro Soto
2022-10-16
Rename cycles as control
Alejandro Soto