| Age | Commit message (Expand) | Author |
|---|---|---|
| 2024-02-20 | rtl: refactor filenames and directory hierarchy | Alejandro Soto |
| 2022-12-16 | Implement branch history (simulation only) | Alejandro Soto |
| 2022-12-16 | Implement prefetch aborts | Alejandro Soto |
| 2022-12-07 | Implement single-stepping | Alejandro Soto |
| 2022-12-06 | Implement breakpoints | Alejandro Soto |
| 2022-11-16 | Implement psr read/write logic | Alejandro Soto |
| 2022-11-15 | Fix false undefined exception | Alejandro Soto |
| 2022-11-13 | Convert core state machines to Quartus-inferring RTL | Alejandro Soto |
| 2022-11-13 | Implement CPU halt | Alejandro Soto |
| 2022-11-09 | Implement reset | Alejandro Soto |
| 2022-11-08 | Register decode output in a new porch stage | Alejandro Soto |
| 2022-11-08 | Refactor decode signals into unified insn_decode struct | Alejandro Soto |
| 2022-11-06 | Split issue logic out of control.sv | Alejandro Soto |
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index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
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