| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2022-09-25 | Implement PSR flag handling | Alejandro Soto | |
| 2022-09-25 | Implement initial cycle control logic | Alejandro Soto | |
| 2022-09-24 | Implement initial decoder | Alejandro Soto | |
| 2022-09-23 | Implement core stub | Alejandro Soto | |
| It only has the fetch stage for now | |||
 |
index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
| summaryrefslogtreecommitdiff |