| Age | Commit message (Expand) | Author |
|---|---|---|
| 2024-05-24 | platform/wavelet3d: allow writes to "flash" over jtag | Alejandro Soto |
| 2024-05-24 | platform/wavelet3d: improve performance of JTAG-over-TCP | Alejandro Soto |
| 2024-05-12 | platform/wavelet3d: implement system dram in simulation | Alejandro Soto |
| 2024-05-12 | platform/wavelet3d: implement JTAG TAP bridge in simulation | Alejandro Soto |
| 2024-04-03 | platform/wavelet3d: implement raster output test | Alejandro Soto |
| 2024-03-25 | platform/wavelet3d: add raster simulation | Alejandro Soto |
| 2024-03-09 | platform/wavelet3d: implement floating-point min/max | Alejandro Soto |
| 2024-03-08 | platform/wavelet3d: implement fpint lanes | Alejandro Soto |
| 2024-03-08 | platform/wavelet3d: refactor fpint pipeline | Alejandro Soto |
| 2024-03-08 | platform/wavelet3d: implement int->float conversion | Alejandro Soto |
| 2024-03-07 | platform/wavelet3d: implement unified fp-integer lane | Alejandro Soto |
| 2024-03-03 | platform/wavelet3d: implement rounded fmul | Alejandro Soto |
| 2024-02-28 | platform/wavelet3d: initial commit | Alejandro Soto |
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index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
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