conspiracion - Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.

Age	Commit message (Expand)	Author
2023-09-30	platform: implement SMP controller	Alejandro Soto
2023-09-29	platform: match SDRAM bandwidth with cache line width	Alejandro Soto
2023-09-29	platform: add CPUs and caches to qsys	Alejandro Soto
2023-09-25	rtl/core, tb: replace bus_master with a new top-level module	Alejandro Soto
2022-12-19	Use 90MHz CPU clock	Alejandro Soto
2022-12-16	Add interrupt controller to Platform Designer	Alejandro Soto
2022-11-17	Bug fixes	JulianCamacho
2022-11-15	Replace vga_controller with streaming Altera IP	Alejandro Soto
2022-11-14	Fix VRAM clock	Alejandro Soto
2022-11-14	Add JTAG debug bridge	Alejandro Soto
2022-11-14	Implement VGA controller	Alejandro Soto
2022-11-13	Restore clock connections in Platform Designer	Alejandro Soto
2022-11-13	Hardwire PLL reset to ground	Alejandro Soto
2022-11-13	Add debug instrumentation	Alejandro Soto
2022-11-09	Fix bus master connections in qsys	Alejandro Soto
2022-11-09	Connect bus master to 50MHz reference clock	Alejandro Soto
2022-11-08	Add hardware debug interfaces	Alejandro Soto
2022-11-03	platform: add vga controller to platform	José Julián
2022-11-02	Fix qsys memory map	Alejandro Soto
2022-11-01	Se modifica el platform design	José Julián
2022-10-15	Rework bus architecture	Alejandro Soto
2022-09-23	Remap top 512MiB of HPS DDR3	Alejandro Soto
2022-09-19	DDR3 is working	Alejandro Soto
2022-09-04	Add Avalon bus master	Alejandro Soto
2022-09-02	Add hps_0 platform design	Alejandro Soto