| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2022-11-02 | Use PLL output as CPU clock | Alejandro Soto | |
| 2022-10-16 | Set core clock target to 100MHz | Alejandro Soto | |
| 2022-09-24 | Fix timing analysis file | Alejandro Soto | |
| 2022-09-19 | Add .sdc for timing analysis | Alejandro Soto | |
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index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
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