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2022-11-15Implement sub-word memory accessesAlejandro Soto
2022-11-15Rename existing MMU components to MMU arbiterAlejandro Soto
2022-11-15Replace vga_controller with streaming Altera IPAlejandro Soto
2022-11-14Add modified Signal Tap testAlejandro Soto
2022-11-13Implement CPU haltAlejandro Soto
2022-11-13Add Signal Tap bus master snifferAlejandro Soto
2022-11-13Add reset debounceAlejandro Soto
2022-11-13Add debug instrumentationAlejandro Soto
2022-11-09Implement initial state randomization in simAlejandro Soto
2022-11-08Add missing toplevel pin connectionsAlejandro Soto
2022-11-08Register decode output in a new porch stageAlejandro Soto
2022-11-07Quartus has not support for unique0Alejandro Soto
2022-11-07Split decode mux logic out of decode.svAlejandro Soto
2022-11-06Implement decode for mrs, msrAlejandro Soto
2022-11-06Move CP15 logic out of control.svAlejandro Soto
2022-11-06Move multiplication logic out of control.svAlejandro Soto
2022-11-06Move load-store logic out of control.svAlejandro Soto
2022-11-06Split regfile read select logic out of control.svAlejandro Soto
2022-11-06Move exception logic out of control.svAlejandro Soto
2022-11-06Split ALU/shifter control logic out of control.svAlejandro Soto
2022-11-06Split branch logic out of control.svAlejandro Soto
2022-11-06Multiplex writeback control signalsAlejandro Soto
2022-11-06Add dsp_mul IP variationAlejandro Soto
2022-11-02Fix qsys memory mapAlejandro Soto
2022-11-01Add CPUID registerAlejandro Soto
2022-11-01Add cp15 primary register mapAlejandro Soto
2022-11-01Add the cp15 subsystemAlejandro Soto
2022-11-01Implement coprocessor instruction decodeAlejandro Soto
2022-11-01Replace decode enable signals with datapath signalsAlejandro Soto
2022-10-31Move mul.sv to rtl/coreAlejandro Soto
2022-10-25Split mux logic out of control.svAlejandro Soto
2022-10-17Break sub-100MHz critical path involving wb_alu_flagsAlejandro Soto
2022-10-16Rename cycles as controlAlejandro Soto
2022-10-16Move isa.sv to core/decodeAlejandro Soto
2022-10-15Rework bus architectureAlejandro Soto
2022-10-08Implement LDR/STR decodeAlejandro Soto
2022-10-02Split decoding of flexible second operand out of data instructionsAlejandro Soto
2022-10-02Make the fetch stage use the bus arbiterAlejandro Soto
2022-10-02Major shifter-ALU redesignAlejandro Soto
The shifter unit now works in parallel with the ALU and is no longer part of it. Instructions that use the shifter as input to the ALU will now take an additional cycle, unless the control unit can detect a "trivial shift" situation where the shifter's output will be the same as its input. This change improves Fmax substantially.
2022-09-25Fix Quartus issuesAlejandro Soto
2022-09-23Add toplevel module for core testsAlejandro Soto
2022-09-19DDR3 is workingAlejandro Soto
2022-09-18Rename data_rw to data_wr in bus masterAlejandro Soto
2022-09-17Update project structure to match Verilator MakefileAlejandro Soto
2022-09-04Add SDRAM testAlejandro Soto
2022-09-02Fix output buffer atom errorsAlejandro Soto
2022-09-02Add hps_0 platform designAlejandro Soto
2022-09-01Initial commitAlejandro Soto
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