| Age | Commit message (Expand) | Author |
|---|---|---|
| 2023-10-05 | bus_test.stp: remove | Alejandro Soto |
| 2022-11-16 | Update bus_test.stp | Alejandro Soto |
| 2022-11-14 | Add modified Signal Tap test | Alejandro Soto |
| 2022-11-13 | Add Signal Tap bus master sniffer | Alejandro Soto |
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index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
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