index
:
conspiracion
master
Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.
summary
refs
log
tree
commit
diff
log msg
author
committer
range
Age
Commit message (
Collapse
)
Author
2022-11-13
Convert core state machines to Quartus-inferring RTL
Alejandro Soto
2022-11-13
Implement CPU halt
Alejandro Soto
2022-11-13
Increment debounce wait time
Alejandro Soto
2022-11-13
Document reset issues
Alejandro Soto
2022-11-13
Add Signal Tap bus master sniffer
Alejandro Soto
2022-11-13
Route cpu_rst_n signal through bus master
Alejandro Soto
2022-11-13
Add reset debounce
Alejandro Soto
2022-11-13
Hardwire PLL reset to ground
Alejandro Soto
2022-11-13
Add debug instrumentation
Alejandro Soto
2022-11-13
Simplify stall conditions to reflect uarch changes
Alejandro Soto
2022-11-10
app: añade aplicación en ASM
Fabián Montero
2022-11-10
Fix fetch discard glitches on flush
Alejandro Soto
2022-11-10
Load taller_bootrom.bin in kermit script
Alejandro Soto
2022-11-10
Implement support for predictable x-values in sim
Alejandro Soto
2022-11-10
Fix reset glitches
Alejandro Soto
2022-11-10
Fix flush-stall relationship in porch
Alejandro Soto
2022-11-09
Improve sdram sim test
Alejandro Soto
2022-11-09
Implement initial state randomization in sim
Alejandro Soto
2022-11-09
Implement reset
Alejandro Soto
2022-11-09
Fix bus master connections in qsys
Alejandro Soto
2022-11-09
Add reset signal to bus master
Alejandro Soto
2022-11-09
Update soc_system.cof
Alejandro Soto
2022-11-09
Fix bus protocol errors in bus master
Alejandro Soto
2022-11-09
Connect bus master to 50MHz reference clock
Alejandro Soto
2022-11-09
Update fetch, decode testbenches
Alejandro Soto
2022-11-08
Fix handling of multi-cycle Avalon waitrequest states in bus master
Alejandro Soto
2022-11-08
Add hardware debug interfaces
Alejandro Soto
2022-11-08
Add sim: sdram
Alejandro Soto
2022-11-08
Add missing toplevel pin connections
Alejandro Soto
2022-11-08
Improve ALU performance
Alejandro Soto
2022-11-08
Register decode output in a new porch stage
Alejandro Soto
2022-11-08
Rename datapath_decode as ctrl_decode
Alejandro Soto
2022-11-08
Refactor decode signals into unified insn_decode struct
Alejandro Soto
2022-11-07
Añade testbench para fetch y decode
JulianCamacho
2022-11-07
Adding decode instructions for test
JulianCamacho
2022-11-07
Adding decode test
JulianCamacho
2022-11-07
Fix flags hazard in ADC, SBC, RSC
Alejandro Soto
2022-11-07
Remove false dependencies on control.issue (long combinational)
Alejandro Soto
2022-11-07
Fix long combinational path between regs and fetch
Alejandro Soto
2022-11-07
Rework regfile in order to remove negedge trigger
Alejandro Soto
2022-11-07
Quartus has not support for unique0
Alejandro Soto
2022-11-07
Add test sim: modeswitch
Alejandro Soto
2022-11-07
Improve mult sim
Alejandro Soto
2022-11-07
Implement multiplication control
Alejandro Soto
2022-11-07
Split decode mux logic out of decode.sv
Alejandro Soto
2022-11-06
Add PSR control signal set
Alejandro Soto
2022-11-06
Implement decode for mrs, msr
Alejandro Soto
2022-11-06
Export PSRs to simulation
Alejandro Soto
2022-11-06
Implement PSR modes and interrupt masks
Alejandro Soto
2022-11-06
Clean-up control.sv
Alejandro Soto
[next]