Fix handling of multi-cycle Avalon waitrequest states in bus master

5 files changed, 14 insertions, 5 deletions

diff --git a/rtl/bus_master.sv b/rtl/bus_master.sv
index 560cb67..ba6096c 100644
--- a/rtl/bus_master.sv
+++ b/rtl/bus_master.sv
@@ -47,7 +47,7 @@ module bus_master
 			end
 
 			WAIT:
-				if(!start)
+				if(!avl_waitrequest)
 					state <= IDLE;
 		endcase
 
diff --git a/tb/mem.cpp b/tb/mem.cpp
index bfbc3ea..6eeb7df 100644
--- a/tb/mem.cpp
+++ b/tb/mem.cpp
@@ -16,7 +16,7 @@ namespace taller::avalon
 	bool mem::read(std::uint32_t addr, std::uint32_t &data)
 	{
 		data = block[addr];
-		return true;
+		return ready();
 	}
 
 	bool mem::write(std::uint32_t addr, std::uint32_t data, unsigned byte_enable)
@@ -44,6 +44,12 @@ namespace taller::avalon
 		}
 
 		block[addr] = (data & bytes) | (block[addr] & ~bytes);
-		return true;
+		return ready();
+	}
+
+	bool mem::ready() noexcept
+	{
+		count = count > 0 ? count - 1 : 2;
+		return count == 0;
 	}
 }
diff --git a/tb/mem.hpp b/tb/mem.hpp
index 016fdc0..a76780d 100644
--- a/tb/mem.hpp
+++ b/tb/mem.hpp
@@ -36,6 +36,9 @@ namespace taller::avalon
 			std::unique_ptr<std::uint32_t[]> block;
 			std::uint32_t                    base;
 			std::uint32_t                    mask;
+			unsigned                         count = 0;
+
+			bool ready() noexcept;
 	};
 
 	template<typename F>
diff --git a/tb/sim/fibonacci.py b/tb/sim/fibonacci.py
index fb20b63..f8bec8a 100644
--- a/tb/sim/fibonacci.py
+++ b/tb/sim/fibonacci.py
@@ -1,7 +1,7 @@
 BASE = 0x0001_0000
 COUNT = 20
 
-cycles = 500
+cycles = 1024
 mem_dumps = [range(BASE, BASE + 4 * COUNT)]
 
 def final():
diff --git a/tb/sim/sdram.py b/tb/sim/sdram.py
index 2225941..fbc2c97 100644
--- a/tb/sim/sdram.py
+++ b/tb/sim/sdram.py
@@ -1,7 +1,7 @@
 START = 0x0000_1000
 END   = 0x0000_2000
 
-cycles = 15000
+cycles = 30000
 mem_dumps = [range(START, END)]
 
 def final():