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AgeCommit message (Collapse)Author
2022-09-25Implement ALUAlejandro Soto
2022-09-25Implement initial cycle control logicAlejandro Soto
2022-09-25Add fetch jump targetAlejandro Soto
2022-09-25Fetch NOP on prefetch flushAlejandro Soto
2022-09-25Implement branch handling in decodeAlejandro Soto
2022-09-25Use word/ptr instead of logic[..]Alejandro Soto
2022-09-25Implement register fileAlejandro Soto
2022-09-24Implement initial decoderAlejandro Soto
2022-09-24Implement decode of branch instructionsAlejandro Soto
2022-09-24Implement decode of ALU instructionsAlejandro Soto
2022-09-24Add instruction encodingsAlejandro Soto
2022-09-24Fix timing analysis fileAlejandro Soto
2022-09-23Add toplevel module for core testsAlejandro Soto
2022-09-23Add initial NixOS expression for boot imageAlejandro Soto
2022-09-23Implement core stubAlejandro Soto
It only has the fetch stage for now
2022-09-23Implement initial fetch stageAlejandro Soto
2022-09-23Rename conspiracion.sv test as hps_sdram_test.svAlejandro Soto
2022-09-23Remap top 512MiB of HPS DDR3Alejandro Soto
2022-09-19Add HPS u-boot scriptAlejandro Soto
2022-09-19Add .cof for conversion to .rbfAlejandro Soto
2022-09-19Add .sdc for timing analysisAlejandro Soto
2022-09-19DDR3 is workingAlejandro Soto
2022-09-18Rename data_rw to data_wr in bus masterAlejandro Soto
2022-09-18Fix public_flat_rw signalsAlejandro Soto
2022-09-18Fix memory simulationAlejandro Soto
2022-09-18Implement Avalon memory module for simulationAlejandro Soto
2022-09-18Update testbenchAlejandro Soto
2022-09-18Add Avalon-MM emulatorAlejandro Soto
2022-09-17Update project structure to match Verilator MakefileAlejandro Soto
2022-09-04Add SDRAM testAlejandro Soto
2022-09-04Add Avalon bus masterAlejandro Soto
2022-09-02Fix output buffer atom errorsAlejandro Soto
2022-09-02Add hps_0 platform designAlejandro Soto
2022-09-01Initial commitAlejandro Soto
generated by cgit v1.2.3 (git 2.25.1) at 2026-04-17 18:42:52 +0000