Initial commit

6 files changed, 168 insertions, 0 deletions

diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..4a27f25
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,35 @@
+*.png
+*.bak
+/db
+/simulation
+/incremental_db
+*.sof
+*.rpt
+*.summary
+*.done
+*.jdi
+*.qdf
+*.cdf
+*.pin
+*.pof
+*.qws
+*.log
+*.chg
+/output_files
+/.sopc_builder
+/sopc_builder_log.txt
+/nios_system_log.txt
+*.html
+*.bsf
+*.ptf.*
+/.metadata
+*.elf
+*.map
+*.objdump
+obj
+*.swp
+*.a
+nios_workspace
+
+vcd/
+obj/
diff --git a/Makefile b/Makefile
new file mode 100644
index 0000000..787efa1
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,28 @@
+TOP       := conspiracion
+VCD_DIR   := vcd
+OBJ_DIR   := obj
+RTL_DIR   := rtl
+TB_DIR    := tb
+VERILATOR := verilator
+
+all: trace
+
+clean:
+	rm -rf $(OBJ_DIR) $(VCD_DIR)
+
+trace: exe vcd
+	cd $(VCD_DIR) && ../$(OBJ_DIR)/V$(TOP)
+
+$(VCD_DIR):
+	@mkdir $(VCD_DIR)
+
+exe: $(OBJ_DIR)/V$(TOP)
+
+$(OBJ_DIR)/V$(TOP): $(OBJ_DIR)/V$(TOP).mk
+	$(MAKE) -C $(OBJ_DIR) -f V$(TOP).mk $(MAKEFLAGS)
+
+$(OBJ_DIR)/V$(TOP).mk: $(wildcard $(RTL_DIR)/*.sv) $(wildcard $(TB_DIR)/*.cpp)
+	$(VERILATOR) \
+		--cc --exe --trace \
+		-y $(RTL_DIR) --Mdir $(OBJ_DIR) \
+		rtl/$(TOP).sv $(wildcard $(TB_DIR)/*.cpp)
diff --git a/conspiracion.qpf b/conspiracion.qpf
new file mode 100644
index 0000000..a1094ef
--- /dev/null
+++ b/conspiracion.qpf
@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2020  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+# Date created = 14:48:15  September 01, 2022
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "20.1"
+DATE = "14:48:15  September 01, 2022"
+
+# Revisions
+
+PROJECT_REVISION = "conspiracion"
diff --git a/conspiracion.qsf b/conspiracion.qsf
new file mode 100644
index 0000000..932b24b
--- /dev/null
+++ b/conspiracion.qsf
@@ -0,0 +1,53 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2020  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+# Date created = 14:48:15  September 01, 2022
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		conspiracion_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus Prime software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name DEVICE 5CSEMA5F31C6
+set_global_assignment -name TOP_LEVEL_ENTITY conspiracion
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:48:15  SEPTEMBER 01, 2022"
+set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
\ No newline at end of file
diff --git a/rtl/conspiracion.sv b/rtl/conspiracion.sv
new file mode 100644
index 0000000..7bb8296
--- /dev/null
+++ b/rtl/conspiracion.sv
@@ -0,0 +1,2 @@
+module conspiracion;
+endmodule
diff --git a/tb/main.cpp b/tb/main.cpp
new file mode 100644
index 0000000..d4bdbcb
--- /dev/null
+++ b/tb/main.cpp
@@ -0,0 +1,19 @@
+#include <verilated.h>
+#include <cstdio>
+
+#include "Vconspiracion.h"
+
+int main(int argc, char **argv)
+{
+    Verilated::commandArgs(argc, argv);   // Remember args
+	Verilated::traceEverOn(true);
+
+	Vconspiracion top;
+    // Do not instead make Vtop as a file-scope static
+    // variable, as the "C++ static initialization order fiasco"
+    // may cause a crash
+
+	top.eval();
+
+    top.final();
+}