| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2022-09-19 | DDR3 is working | Alejandro Soto | |
| 2022-09-18 | Rename data_rw to data_wr in bus master | Alejandro Soto | |
| 2022-09-18 | Fix public_flat_rw signals | Alejandro Soto | |
| 2022-09-18 | Fix memory simulation | Alejandro Soto | |
| 2022-09-18 | Implement Avalon memory module for simulation | Alejandro Soto | |
| 2022-09-18 | Update testbench | Alejandro Soto | |
| 2022-09-18 | Add Avalon-MM emulator | Alejandro Soto | |
| 2022-09-17 | Update project structure to match Verilator Makefile | Alejandro Soto | |
| 2022-09-04 | Add SDRAM test | Alejandro Soto | |
| 2022-09-04 | Add Avalon bus master | Alejandro Soto | |
| 2022-09-02 | Fix output buffer atom errors | Alejandro Soto | |
| 2022-09-02 | Add hps_0 platform design | Alejandro Soto | |
| 2022-09-01 | Initial commit | Alejandro Soto | |
 |
index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
| summaryrefslogtreecommitdiff |