conspiracion - Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.

Age	Commit message (Expand)	Author
2022-09-25	Fetch NOP on prefetch flush	Alejandro Soto
2022-09-25	Implement branch handling in decode	Alejandro Soto
2022-09-25	Use word/ptr instead of logic[..]	Alejandro Soto
2022-09-25	Implement register file	Alejandro Soto
2022-09-24	Implement initial decoder	Alejandro Soto
2022-09-24	Implement decode of branch instructions	Alejandro Soto
2022-09-24	Implement decode of ALU instructions	Alejandro Soto
2022-09-24	Add instruction encodings	Alejandro Soto
2022-09-24	Fix timing analysis file	Alejandro Soto
2022-09-23	Add toplevel module for core tests	Alejandro Soto
2022-09-23	Add initial NixOS expression for boot image	Alejandro Soto
2022-09-23	Implement core stub	Alejandro Soto
2022-09-23	Implement initial fetch stage	Alejandro Soto
2022-09-23	Rename conspiracion.sv test as hps_sdram_test.sv	Alejandro Soto
2022-09-23	Remap top 512MiB of HPS DDR3	Alejandro Soto
2022-09-19	Add HPS u-boot script	Alejandro Soto
2022-09-19	Add .cof for conversion to .rbf	Alejandro Soto
2022-09-19	Add .sdc for timing analysis	Alejandro Soto
2022-09-19	DDR3 is working	Alejandro Soto
2022-09-18	Rename data_rw to data_wr in bus master	Alejandro Soto
2022-09-18	Fix public_flat_rw signals	Alejandro Soto
2022-09-18	Fix memory simulation	Alejandro Soto
2022-09-18	Implement Avalon memory module for simulation	Alejandro Soto
2022-09-18	Update testbench	Alejandro Soto
2022-09-18	Add Avalon-MM emulator	Alejandro Soto
2022-09-17	Update project structure to match Verilator Makefile	Alejandro Soto
2022-09-04	Add SDRAM test	Alejandro Soto
2022-09-04	Add Avalon bus master	Alejandro Soto
2022-09-02	Fix output buffer atom errors	Alejandro Soto
2022-09-02	Add hps_0 platform design	Alejandro Soto
2022-09-01	Initial commit	Alejandro Soto