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-rwxr-xr-xsim/sim.py7
1 files changed, 5 insertions, 2 deletions
diff --git a/sim/sim.py b/sim/sim.py
index be846fb..b0a194a 100755
--- a/sim/sim.py
+++ b/sim/sim.py
@@ -275,13 +275,16 @@ prelude.update({k: v for k, v in all_regs})
module.__dict__.update(prelude)
spec.loader.exec_module(module)
-cycles = module_get('cycles', 1024)
mem_dumps = module_get('mem_dumps', [])
if init := module_get('init'):
init()
-exec_args = [verilated, '--headless', '--no-tty', '--cycles', str(cycles), '--dump-regs']
+exec_args = [verilated, '--headless', '--no-tty', '--dump-regs']
+
+cycles = module_get('cycles', 1024)
+if cycles is not None:
+ exec_args.extend(['--cycles', str(cycles)])
for rng in mem_dumps:
length = rng.stop - rng.start