3 files changed, 17 insertions, 10 deletions
diff --git a/rtl/core/arm810.sv b/rtl/core/arm810.sv
index 5525f95..d66ac72 100644
--- a/rtl/core/arm810.sv
+++ b/rtl/core/arm810.sv
@@ -21,7 +21,6 @@ module arm810
 	(
 		.branch(explicit_branch || wr_pc),
 		.flush(0), //TODO
-		.target(wr_pc ? wr_value[31:2] : branch_target),
 		.addr(insn_addr),
 		.fetched(insn_ready),
 		.fetch_data(insn_data_rd),
@@ -92,7 +91,7 @@ module arm810
 	);
 
 	logic wr_pc;
-	word rd_value_a, rd_value_b;
+	word rd_value_a, rd_value_b, wr_current;
 
 	core_regs regs
 	(
diff --git a/rtl/core/fetch/fetch.sv b/rtl/core/fetch/fetch.sv
index c1f150c..d938699 100644
--- a/rtl/core/fetch/fetch.sv
+++ b/rtl/core/fetch/fetch.sv
@@ -8,8 +8,10 @@ module core_fetch
 	             branch,
 	             flush,
 	             fetched,
-	input  word  fetch_data,
-	input  ptr   target,
+	             wr_pc,
+	input  ptr   branch_target,
+	input  word  wr_current,
+	             fetch_data,
 
 	output logic fetch,
 	output word  insn,
@@ -17,9 +19,10 @@ module core_fetch
 	             addr
 );
 
-	ptr next_pc, head, hold_addr;
+	ptr next_pc, head, hold_addr, target;
 	logic fetched_valid, do_flush, discard;
 
+	assign target = wr_pc ? wr_current[31:2] : branch_target; //TODO: alignment exception
 	assign do_flush = branch || flush;
 	assign fetched_valid = fetched && !discard;
 
@@ -52,8 +55,8 @@ module core_fetch
 	end
 
 	initial begin
-		hold_addr = 0;
 		discard = 0;
+		hold_addr = 0;
 	end
 
 endmodule
diff --git a/rtl/core/regs/regs.sv b/rtl/core/regs/regs.sv
index b25a122..9cf7033 100644
--- a/rtl/core/regs/regs.sv
+++ b/rtl/core/regs/regs.sv
@@ -14,6 +14,7 @@ module core_regs
 
 	output word     rd_value_a,
 	                rd_value_b,
+	                wr_current,
 	output logic    branch
 );
 
@@ -23,11 +24,10 @@ module core_regs
 	 * sincronizadas del archivo de registros.
 	 */
 
-	word pc_word, wr_current;
+	word pc_word;
 	logic wr_pc, wr_enable_file;
 	reg_index wr_index;
 
-	assign branch = wr_enable && wr_pc;
 	assign pc_word = {pc_visible, 2'b00};
 	assign wr_enable_file = wr_enable && !wr_pc;
 
@@ -53,11 +53,16 @@ module core_regs
 		.index(wr_index)
 	);
 
-	always_ff @(posedge clk)
+	always_ff @(posedge clk) begin
 		if(wr_enable)
 			wr_current <= wr_value;
 
-	initial
+		branch <= wr_enable && wr_pc;
+	end
+
+	initial begin
+		branch = 0;
 		wr_current = 0;
+	end
 
 endmodule