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Diffstat (limited to 'rtl/dma_axi32/prgen_min2.v')
| -rw-r--r-- | rtl/dma_axi32/prgen_min2.v | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/rtl/dma_axi32/prgen_min2.v b/rtl/dma_axi32/prgen_min2.v new file mode 100644 index 0000000..7788bb7 --- /dev/null +++ b/rtl/dma_axi32/prgen_min2.v @@ -0,0 +1,55 @@ +/////////////////////////////////////////////////////////////////////
+//// ////
+//// Author: Eyal Hochberg ////
+//// eyal@provartec.com ////
+//// ////
+//// Downloaded from: http://www.opencores.org ////
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2010 Provartec LTD ////
+//// www.provartec.com ////
+//// info@provartec.com ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation.////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more////
+//// details. http://www.gnu.org/licenses/lgpl.html ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+//--------------------------------------------------------- +//-- File generated by RobustVerilog parser +//-- Version: 1.0 +//-- Invoked Fri Mar 25 23:34:53 2011 +//-- +//-- Source file: prgen_min2.v +//--------------------------------------------------------- + + + +module prgen_min2(a,b,min); + + parameter WIDTH = 8; + + input [WIDTH-1:0] a; + input [WIDTH-1:0] b; + + output [WIDTH-1:0] min; + + + assign min = a < b ? a : b; + +endmodule + + + + |
