diff options
Diffstat (limited to 'rtl/core')
| -rw-r--r-- | rtl/core/bus_master.sv | 74 | ||||
| -rw-r--r-- | rtl/core/core.sv | 99 |
2 files changed, 111 insertions, 62 deletions
diff --git a/rtl/core/bus_master.sv b/rtl/core/bus_master.sv new file mode 100644 index 0000000..39c4893 --- /dev/null +++ b/rtl/core/bus_master.sv @@ -0,0 +1,74 @@ +`include "core/uarch.sv" + +module bus_master +( + input logic clk, + rst_n, + + output word avl_address, + output logic avl_read, + avl_write, + avl_lock, + input word avl_readdata, + output word avl_writedata, + input logic avl_waitrequest, + input logic[1:0] avl_response, + output logic[3:0] avl_byteenable, + + input logic start, + write, + ex_lock, + input ptr addr, + input logic[3:0] data_be, + input word data_wr, + output logic ready, + ex_fail, + output word data_rd +); + + enum int unsigned + { + IDLE, + WAIT + } state; + + assign data_rd = avl_readdata; + assign ex_fail = |avl_response; + + always_comb + unique case (state) + IDLE: ready = 0; + WAIT: ready = !avl_waitrequest; + endcase + + always_ff @(posedge clk or negedge rst_n) + /* P. 16: + * A host must make no assumption about the assertion state of + * waitrequest when the host is idle: waitrequest may be high or + * low, depending on system properties. When waitrequest is asserted, + * host control signals to the agent must remain constant except for + * beginbursttransfer. + */ + if(!rst_n) begin + state <= IDLE; + avl_lock <= 0; + avl_read <= 0; + avl_write <= 0; + avl_address <= 0; + avl_writedata <= 0; + avl_byteenable <= 0; + end else if ((state == IDLE || !avl_waitrequest) && start) begin + state <= WAIT; + avl_lock <= ex_lock; + avl_read <= ~write; + avl_write <= write; + avl_address <= {addr, 2'b00}; + avl_writedata <= data_wr; + avl_byteenable <= write ? data_be : 4'b1111; + end else if(state == WAIT && !avl_waitrequest) begin + state <= IDLE; + avl_read <= 0; + avl_write <= 0; + end + +endmodule diff --git a/rtl/core/core.sv b/rtl/core/core.sv index 3b87298..ce51a71 100644 --- a/rtl/core/core.sv +++ b/rtl/core/core.sv @@ -1,6 +1,8 @@ `include "core/uarch.sv" +`include "config.sv" module core +#(parameter ID=0) ( input logic clk, rst_n, @@ -23,72 +25,45 @@ module core input logic avl_irq ); - logic ex_fail, ex_lock, start, ready, write; + generate + if (ID < `CONFIG_CPUS) begin: enable + ptr addr; + word data_wr; + logic start, write; + logic[3:0] data_be; - logic[3:0] data_be; - logic[29:0] addr; - logic[31:0] data_rd, data_wr; + arm810 cpu + ( + .irq(avl_irq), + .halt(cpu_halt), + .halted(cpu_halted), + .bus_addr(addr), + .bus_data_rd(data_rd), + .bus_data_wr(data_wr), + .bus_data_be(data_be), + .bus_ready(ready), + .bus_write(write), + .bus_start(start), + .bus_ex_fail(ex_fail), + .bus_ex_lock(ex_lock), + .* + ); - enum int unsigned - { - IDLE, - WAIT - } state; + word data_rd; + logic ex_fail, ex_lock, ready; - arm810 cpu - ( - .irq(avl_irq), - .halt(cpu_halt), - .halted(cpu_halted), - .bus_addr(addr), - .bus_data_rd(data_rd), - .bus_data_wr(data_wr), - .bus_data_be(data_be), - .bus_ready(ready), - .bus_write(write), - .bus_start(start), - .bus_ex_fail(ex_fail), - .bus_ex_lock(ex_lock), - .* - ); + bus_master master + ( + .* + ); + end else begin + assign cpu_halted = 1; + assign breakpoint = 0; - assign data_rd = avl_readdata; - assign ex_fail = |avl_response; - - always_comb - unique case(state) - IDLE: ready = 0; - WAIT: ready = !avl_waitrequest; - endcase - - always_ff @(posedge clk or negedge rst_n) - /* P. 16: - * A host must make no assumption about the assertion state of - * waitrequest when the host is idle: waitrequest may be high or - * low, depending on system properties. When waitrequest is asserted, - * host control signals to the agent must remain constant except for - * beginbursttransfer. - */ - if(!rst_n) begin - state <= IDLE; - avl_lock <= 0; - avl_read <= 0; - avl_write <= 0; - avl_address <= 0; - avl_writedata <= 0; - avl_byteenable <= 0; - end else if((state == IDLE || !avl_waitrequest) && start) begin - state <= WAIT; - avl_lock <= ex_lock; - avl_read <= ~write; - avl_write <= write; - avl_address <= {addr, 2'b00}; - avl_writedata <= data_wr; - avl_byteenable <= write ? data_be : 4'b1111; - end else if(state == WAIT && !avl_waitrequest) begin - state <= IDLE; - avl_read <= 0; - avl_write <= 0; + assign avl_lock = 0; + assign avl_read = 0; + assign avl_write = 0; end + endgenerate endmodule |