diff options
Diffstat (limited to 'rtl/core')
| -rw-r--r-- | rtl/core/control/data.sv | 30 | ||||
| -rw-r--r-- | rtl/core/control/ldst/ldst.sv | 21 | ||||
| -rw-r--r-- | rtl/core/control/mul.sv | 17 | ||||
| -rw-r--r-- | rtl/core/control/select.sv | 14 | ||||
| -rw-r--r-- | rtl/core/control/writeback.sv | 3 |
5 files changed, 40 insertions, 45 deletions
diff --git a/rtl/core/control/data.sv b/rtl/core/control/data.sv index 5fa6db9..320747f 100644 --- a/rtl/core/control/data.sv +++ b/rtl/core/control/data.sv @@ -15,7 +15,6 @@ module core_control_data input ctrl_cycle cycle, next_cycle, - input logic issue, input ptr pc, input word mem_offset, input psr_flags flags, @@ -66,21 +65,20 @@ module core_control_data always_ff @(posedge clk) unique case(next_cycle) - ISSUE: - if(issue) begin - alu <= dec_data.op; - c_in <= flags.c; - - data_snd_is_imm <= dec_snd.is_imm; - data_snd_shift_by_reg <= dec_snd.shift_by_reg; - data_imm <= dec_snd.imm; - data_shift_imm <= dec_snd.shift_imm; - - shifter.shr <= dec_snd.shr; - shifter.ror <= dec_snd.ror; - shifter.put_carry <= dec_snd.put_carry; - shifter.sign_extend <= dec_snd.sign_extend; - end + ISSUE: begin + alu <= dec_data.op; + c_in <= flags.c; + + data_snd_is_imm <= dec_snd.is_imm; + data_snd_shift_by_reg <= dec_snd.shift_by_reg; + data_imm <= dec_snd.imm; + data_shift_imm <= dec_snd.shift_imm; + + shifter.shr <= dec_snd.shr; + shifter.ror <= dec_snd.ror; + shifter.put_carry <= dec_snd.put_carry; + shifter.sign_extend <= dec_snd.sign_extend; + end RD_INDIRECT_SHIFT: begin saved_base <= rd_value_b; diff --git a/rtl/core/control/ldst/ldst.sv b/rtl/core/control/ldst/ldst.sv index 0a2f6c9..c8dac7c 100644 --- a/rtl/core/control/ldst/ldst.sv +++ b/rtl/core/control/ldst/ldst.sv @@ -46,18 +46,19 @@ module core_control_ldst always_ff @(posedge clk) unique case(next_cycle) - ISSUE: - if(issue) begin - // TODO: dec_ldst.unprivileged/user_regs - // TODO: byte/halfword sizes + ISSUE: begin + // TODO: dec_ldst.unprivileged/user_regs + // TODO: byte/halfword sizes + if(issue) ldst <= dec.ldst; - ldst_pre <= dec_ldst.pre_indexed; - ldst_increment <= dec_ldst.increment; - ldst_writeback <= dec_ldst.writeback; - mem_regs <= dec_ldst.regs; - mem_write <= !dec_ldst.load; - end + ldst_pre <= dec_ldst.pre_indexed; + ldst_increment <= dec_ldst.increment; + ldst_writeback <= dec_ldst.writeback; + + mem_regs <= dec_ldst.regs; + mem_write <= !dec_ldst.load; + end TRANSFER: begin if(cycle != TRANSFER) begin diff --git a/rtl/core/control/mul.sv b/rtl/core/control/mul.sv index c3625f8..5377045 100644 --- a/rtl/core/control/mul.sv +++ b/rtl/core/control/mul.sv @@ -36,15 +36,14 @@ module core_control_mul mul_start <= 0; unique case(next_cycle) - ISSUE: - if(issue) begin - mul <= dec.mul; - mul_add <= dec_mul.add; - mul_long <= dec_mul.long_mul; - mul_signed <= dec_mul.signed_mul; - mul_r_add_hi <= dec_mul.r_add_hi; - mul_r_add_lo <= dec_mul.r_add_lo; - end + ISSUE: begin + mul <= issue && dec.mul; + mul_add <= dec_mul.add; + mul_long <= dec_mul.long_mul; + mul_signed <= dec_mul.signed_mul; + mul_r_add_hi <= dec_mul.r_add_hi; + mul_r_add_lo <= dec_mul.r_add_lo; + end MUL: mul_start <= cycle != MUL; diff --git a/rtl/core/control/select.sv b/rtl/core/control/select.sv index 3c0ec6c..62ad503 100644 --- a/rtl/core/control/select.sv +++ b/rtl/core/control/select.sv @@ -9,8 +9,7 @@ module core_control_select input ctrl_cycle cycle, next_cycle, - input logic issue, - mem_ready, + input logic mem_ready, pop_valid, input reg_num popped, final_rd, @@ -31,11 +30,10 @@ module core_control_select rb = last_rb; unique case(next_cycle) - ISSUE: - if(issue) begin - ra = dec_data.rn; - rb = dec_snd.r; - end + ISSUE: begin + ra = dec_data.rn; + rb = dec_snd.r; + end TRANSFER: if(cycle != TRANSFER || mem_ready) @@ -53,7 +51,7 @@ module core_control_select last_ra <= ra; last_rb <= rb; - if(next_cycle == ISSUE && issue) + if(next_cycle == ISSUE) r_shift <= dec_snd.r_shift; end diff --git a/rtl/core/control/writeback.sv b/rtl/core/control/writeback.sv index a4465ff..6506ae5 100644 --- a/rtl/core/control/writeback.sv +++ b/rtl/core/control/writeback.sv @@ -108,8 +108,7 @@ module core_control_writeback unique case(next_cycle) ISSUE: - if(issue) - final_rd <= dec_data.rd; + final_rd <= dec_data.rd; TRANSFER: if((cycle != TRANSFER || mem_ready) && pop_valid) |