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-rw-r--r--rtl/core/uarch.sv26
1 files changed, 19 insertions, 7 deletions
diff --git a/rtl/core/uarch.sv b/rtl/core/uarch.sv
index 1ba039e..be67bd5 100644
--- a/rtl/core/uarch.sv
+++ b/rtl/core/uarch.sv
@@ -17,12 +17,24 @@ typedef logic[29:0] ptr;
*/
typedef logic[4:0] reg_index;
-typedef enum logic[1:0]
-{
- ALU_ADD,
- ALU_AND,
- ALU_ORR,
- ALU_XOR
-} alu_op;
+typedef logic[3:0] alu_op;
+
+// Coincide con campo respectivo de instrucciones de procesamiento de datos
+`define ALU_AND 4'b0000
+`define ALU_EOR 4'b0001
+`define ALU_SUB 4'b0010
+`define ALU_RSB 4'b0011
+`define ALU_ADD 4'b0100
+`define ALU_ADC 4'b0101
+`define ALU_SBC 4'b0110
+`define ALU_RSC 4'b0111
+`define ALU_TST 4'b1000
+`define ALU_TEQ 4'b1001
+`define ALU_CMP 4'b1010
+`define ALU_CMN 4'b1011
+`define ALU_ORR 4'b1100
+`define ALU_MOV 4'b1101
+`define ALU_BIC 4'b1110
+`define ALU_MVN 4'b1111
`endif