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-rw-r--r--rtl/core/cp15/cache_lockdown.sv18
-rw-r--r--rtl/core/cp15/cache_ops.sv15
-rw-r--r--rtl/core/cp15/cp15.sv144
-rw-r--r--rtl/core/cp15/cpuid.sv70
-rw-r--r--rtl/core/cp15/cyclecnt.sv23
-rw-r--r--rtl/core/cp15/domain.sv24
-rw-r--r--rtl/core/cp15/far.sv31
-rw-r--r--rtl/core/cp15/fsr.sv43
-rw-r--r--rtl/core/cp15/map.sv127
-rw-r--r--rtl/core/cp15/syscfg.sv68
-rw-r--r--rtl/core/cp15/tlb.sv15
-rw-r--r--rtl/core/cp15/tlb_lockdown.sv18
-rw-r--r--rtl/core/cp15/ttbr.sv45
13 files changed, 0 insertions, 641 deletions
diff --git a/rtl/core/cp15/cache_lockdown.sv b/rtl/core/cp15/cache_lockdown.sv
deleted file mode 100644
index 65d4c0f..0000000
--- a/rtl/core/cp15/cache_lockdown.sv
+++ /dev/null
@@ -1,18 +0,0 @@
-`include "core/uarch.sv"
-
-module core_cp15_cache_lockdown
-(
- input logic clk,
- rst_n,
-
- input logic load,
- transfer,
- input word write,
-
- output word read
-);
-
- //TODO, aunque al parecer Linux no usa esto
- assign read = 0;
-
-endmodule
diff --git a/rtl/core/cp15/cache_ops.sv b/rtl/core/cp15/cache_ops.sv
deleted file mode 100644
index cb6d4ad..0000000
--- a/rtl/core/cp15/cache_ops.sv
+++ /dev/null
@@ -1,15 +0,0 @@
-`include "core/uarch.sv"
-
-module core_cp15_cache
-(
- input logic clk,
- rst_n,
-
- input logic load,
- transfer,
- input word write
-);
-
- //TODO
-
-endmodule
diff --git a/rtl/core/cp15/cp15.sv b/rtl/core/cp15/cp15.sv
deleted file mode 100644
index 5a482d4..0000000
--- a/rtl/core/cp15/cp15.sv
+++ /dev/null
@@ -1,144 +0,0 @@
-`include "core/cp15/map.sv"
-`include "core/mmu/format.sv"
-`include "core/uarch.sv"
-
-module core_cp15
-(
- input logic clk,
- rst_n,
- transfer,
- input coproc_decode dec,
- input word write,
-
- input logic halt,
- fault_register,
- fault_page,
- input ptr fault_addr,
- input mmu_fault_type fault_type,
- input mmu_domain fault_domain,
-
- output word read,
- mmu_dac,
- output logic high_vectors,
- mmu_enable,
- output mmu_base mmu_ttbr
-);
-
- logic load;
- reg_num crn, crm;
- cp_opcode op1, op2;
-
- assign {crn, crm} = {dec.crn, dec.crm};
- assign {op1, op2} = {dec.op1, dec.op2};
- assign load = dec.load;
-
- word read_cpuid, read_syscfg, read_ttbr, read_domain, read_far,
- read_fsr, read_cache_lockdown, read_tlb_lockdown, read_cyclecnt;
-
- core_cp15_cpuid cpuid
- (
- .read(read_cpuid),
- .*
- );
-
- core_cp15_syscfg syscfg
- (
- .read(read_syscfg),
- .transfer(transfer && crn == `CP15_CRN_SYSCFG),
- .*
- );
-
- core_cp15_ttbr ttbr
- (
- .read(read_ttbr),
- .transfer(transfer && crn == `CP15_CRN_TTBR),
- .*
- );
-
- core_cp15_domain domain
- (
- .read(read_domain),
- .transfer(transfer && crn == `CP15_CRN_DOMAIN),
- .*
- );
-
- core_cp15_far far_
- (
- .read(read_far),
- .transfer(transfer && crn == `CP15_CRN_FAR),
- .*
- );
-
- core_cp15_fsr fsr
- (
- .read(read_fsr),
- .transfer(transfer && crn == `CP15_CRN_FSR),
- .*
- );
-
- core_cp15_cache cache
- (
- .transfer(transfer && crn == `CP15_CRN_CACHE),
- .*
- );
-
- core_cp15_tlb tlb
- (
- .transfer(transfer && crn == `CP15_CRN_TLB),
- .*
- );
-
- core_cp15_cache_lockdown cache_lockdown
- (
- .read(read_cache_lockdown),
- .transfer(transfer && crn == `CP15_CRN_CACHE_LCK),
- .*
- );
-
- core_cp15_tlb_lockdown tlb_lockdown
- (
- .read(read_tlb_lockdown),
- .transfer(transfer && crn == `CP15_CRN_TLB_LCK),
- .*
- );
-
- core_cp15_cyclecnt cyclecnt
- (
- .read(read_cyclecnt),
- .*
- );
-
- always_comb
- unique case(crn)
- `CP15_CRN_CPUID:
- read = read_cpuid;
-
- `CP15_CRN_SYSCFG:
- read = read_syscfg;
-
- `CP15_CRN_TTBR:
- read = read_ttbr;
-
- `CP15_CRN_DOMAIN:
- read = read_domain;
-
- `CP15_CRN_FAR:
- read = read_far;
-
- `CP15_CRN_FSR:
- read = read_fsr;
-
- `CP15_CRN_CACHE_LCK:
- read = read_cache_lockdown;
-
- `CP15_CRN_TLB_LCK:
- read = read_tlb_lockdown;
-
- `CP15_CRN_CYCLECNT:
- read = read_cyclecnt;
-
- default:
- read = {$bits(read){1'bx}};
- endcase
-
-endmodule
diff --git a/rtl/core/cp15/cpuid.sv b/rtl/core/cp15/cpuid.sv
deleted file mode 100644
index c9cab59..0000000
--- a/rtl/core/cp15/cpuid.sv
+++ /dev/null
@@ -1,70 +0,0 @@
-`include "core/uarch.sv"
-`include "core/cp15/map.sv"
-
-module core_cp15_cpuid
-(
- input cp_opcode op2,
- output word read
-);
-
- /* ARM810.pdf, p. 104: Reading from CP15 register 0 returns
- * the value 0x4101810x.
- */
- cp15_cpuid_main main;
- assign main.implementor = 8'h41; // 'A' (ARM)
- assign main.variant = 4'h0;
- assign main.architecture = 4'h1; // ARMv4 (no Thumb)
- assign main.part_number = 12'h810;
- assign main.revision = 4'h0;
-
- cp15_cpuid_cache cache;
- assign cache.mbz = 3'b000;
- assign cache.ctype = 4'b0001; // Write-back, range ops not supported
- assign cache.s = 1; // Split instruction and data caches
- assign cache.dsize = cachesize;
- assign cache.isize = cachesize;
-
- cp15_cpuid_cache_size cachesize;
- assign cachesize.p = 0;
- assign cachesize.mbz = 0;
- assign cachesize.size = 4'b0100; // 8KiB
- assign cachesize.assoc = 3'b001; // 2-way associative
- assign cachesize.m = 0;
- assign cachesize.len = 2'b10; // 32-byte cache lines
-
- cp15_cpuid_tcm tcm;
- assign tcm = 0;
-
- cp15_cpuid_tlb tlb;
- assign tlb.sbz0 = 8'd0;
- assign tlb.ilsize = 8'd0;
- assign tlb.dlsize = 8'd0;
- assign tlb.sbz1 = 7'd0;
- assign tlb.s = 1;
-
- cp15_cpuid_mpu mpu;
- assign mpu = 0;
-
- always_comb
- unique case(op2)
- `CP15_CPUID_CACHE:
- read = cache;
-
- `CP15_CPUID_TCM:
- read = tcm;
-
- `CP15_CPUID_TLB:
- read = tlb;
-
- `CP15_CPUID_MPU:
- read = mpu;
-
- /* If an <opcode2> value corresponding to an unimplemented or
- * reserved ID register is encountered, the System Control
- * coprocessor returns the value of the main ID register.
- */
- default:
- read = main;
- endcase
-
-endmodule
diff --git a/rtl/core/cp15/cyclecnt.sv b/rtl/core/cp15/cyclecnt.sv
deleted file mode 100644
index b079a1b..0000000
--- a/rtl/core/cp15/cyclecnt.sv
+++ /dev/null
@@ -1,23 +0,0 @@
-`include "core/uarch.sv"
-
-module core_cp15_cyclecnt
-(
- input logic clk,
- rst_n,
-
- input logic halt,
-
- output word read
-);
-
- word cyclecnt;
-
- assign read = cyclecnt;
-
- always @(posedge clk or negedge rst_n)
- if(!rst_n)
- cyclecnt <= 0;
- else if(!halt)
- cyclecnt <= cyclecnt + 1;
-
-endmodule
diff --git a/rtl/core/cp15/domain.sv b/rtl/core/cp15/domain.sv
deleted file mode 100644
index de37de4..0000000
--- a/rtl/core/cp15/domain.sv
+++ /dev/null
@@ -1,24 +0,0 @@
-`include "core/uarch.sv"
-
-module core_cp15_domain
-(
- input logic clk,
- rst_n,
-
- input logic load,
- transfer,
- input word write,
-
- output word read,
- mmu_dac /*verilator public*/
-);
-
- assign read = mmu_dac;
-
- always @(posedge clk or negedge rst_n)
- if(!rst_n)
- mmu_dac <= 0;
- else if(transfer && !load)
- mmu_dac <= write;
-
-endmodule
diff --git a/rtl/core/cp15/far.sv b/rtl/core/cp15/far.sv
deleted file mode 100644
index 36e76db..0000000
--- a/rtl/core/cp15/far.sv
+++ /dev/null
@@ -1,31 +0,0 @@
-`include "core/uarch.sv"
-`include "core/cp15/map.sv"
-
-module core_cp15_far
-(
- input logic clk,
- rst_n,
-
- input logic load,
- transfer,
- input word write,
-
- input logic fault_register,
- input ptr fault_addr,
-
- output word read /*verilator public*/
-);
-
- word far;
-
- assign read = far;
-
- always @(posedge clk or negedge rst_n)
- if(!rst_n)
- far <= 0;
- else if(fault_register)
- far <= {fault_addr, 2'b00};
- else if(transfer && !load)
- far <= write;
-
-endmodule
diff --git a/rtl/core/cp15/fsr.sv b/rtl/core/cp15/fsr.sv
deleted file mode 100644
index 81b4992..0000000
--- a/rtl/core/cp15/fsr.sv
+++ /dev/null
@@ -1,43 +0,0 @@
-`include "core/cp15/map.sv"
-`include "core/mmu/format.sv"
-`include "core/uarch.sv"
-
-module core_cp15_fsr
-(
- input logic clk,
- rst_n,
-
- input logic load,
- transfer,
- input word write,
-
- input logic fault_register,
- fault_page,
- input mmu_fault_type fault_type,
- input mmu_domain fault_domain,
-
- output word read /*verilator public*/
-);
-
- logic fsr_page;
- mmu_domain fsr_domain;
- mmu_fault_type fsr_type;
-
- assign read = {24'd0, fsr_domain, fsr_type, fsr_page, 1'b1};
-
- always @(posedge clk or negedge rst_n)
- if(!rst_n) begin
- fsr_page <= 0;
- fsr_type <= 0;
- fsr_domain <= 0;
- end else if(fault_register) begin
- fsr_page <= fault_page;
- fsr_type <= fault_type;
- fsr_domain <= fault_domain;
- end else if(transfer && !load) begin
- fsr_page <= write[1];
- fsr_type <= write[3:2];
- fsr_domain <= write[7:4];
- end
-
-endmodule
diff --git a/rtl/core/cp15/map.sv b/rtl/core/cp15/map.sv
deleted file mode 100644
index 438a5bf..0000000
--- a/rtl/core/cp15/map.sv
+++ /dev/null
@@ -1,127 +0,0 @@
-`ifndef CORE_CP15_MAP_SV
-`define CORE_CP15_MAP_SV
-
-`define CP15_CRN_CPUID 4'd0
-`define CP15_CRN_SYSCFG 4'd1
-`define CP15_CRN_TTBR 4'd2
-`define CP15_CRN_DOMAIN 4'd3
-`define CP15_CRN_FSR 4'd5
-`define CP15_CRN_FAR 4'd6
-`define CP15_CRN_CACHE 4'd7
-`define CP15_CRN_TLB 4'd8
-`define CP15_CRN_CACHE_LCK 4'd9
-`define CP15_CRN_TLB_LCK 4'd10
-`define CP15_CRN_DMA 4'd11
-`define CP15_CRN_PID 4'd13
-`define CP15_CRN_CYCLECNT 4'd15
-
-typedef struct packed
-{
- logic[31:24] implementor;
- logic[23:20] variant;
- logic[19:16] architecture;
- logic[15:4] part_number;
- logic[3:0] revision;
-} cp15_cpuid_main;
-
-`define CP15_CPUID_CACHE 3'b001
-
-typedef struct packed
-{
- logic[11:11] p;
- logic[10:10] mbz;
- logic[9:6] size;
- logic[5:3] assoc;
- logic[2:2] m;
- logic[1:0] len;
-} cp15_cpuid_cache_size;
-
-typedef struct packed
-{
- logic[31:29] mbz;
- logic[28:25] ctype;
- logic[24:24] s;
- cp15_cpuid_cache_size dsize,
- isize;
-} cp15_cpuid_cache;
-
-`define CP15_CPUID_TCM 3'b010
-
-typedef struct packed
-{
- logic[31:29] mbz;
- logic[28:19] sbz0;
- logic[18:16] dtcm;
- logic[15:3] sbz1;
- logic[2:0] itcm;
-} cp15_cpuid_tcm;
-
-`define CP15_CPUID_TLB 3'b011
-
-typedef struct packed
-{
- logic[31:24] sbz0;
- logic[23:16] ilsize;
- logic[15:8] dlsize;
- logic[7:1] sbz1;
- logic[0:0] s;
-} cp15_cpuid_tlb;
-
-`define CP15_CPUID_MPU 3'b100
-
-typedef struct packed
-{
- logic[31:24] sbz0;
- logic[23:16] iregion;
- logic[15:8] dregion;
- logic[7:1] sbz1;
- logic[0:0] s;
-} cp15_cpuid_mpu;
-
-`define CP15_SYSCFG_CTRL 3'b000
-
-typedef struct packed
-{
- logic[31:27] reserved;
- logic[26:26] l2;
- logic[25:25] ee;
- logic[24:24] ve;
- logic[23:23] xp;
- logic[22:22] u;
- logic[21:21] fi;
- logic[20:20] st;
- logic[19:19] sbz0;
- logic[18:18] it;
- logic[17:17] sbz1;
- logic[16:16] dt;
- logic[15:15] l4;
- logic[14:14] rr;
- logic[13:13] v;
- logic[12:12] i;
- logic[11:11] z;
- logic[10:10] f;
- logic[9:9] r;
- logic[8:8] s;
- logic[7:7] b;
- logic[6:6] l;
- logic[5:5] d;
- logic[4:4] p;
- logic[3:3] w;
- logic[2:2] c;
- logic[1:1] a;
- logic[0:0] m;
-} cp15_syscfg_ctrl;
-
-`define CP15_SYSCFG_ACCESS 3'b010
-
-typedef struct packed
-{
- logic[31:14] base;
- logic[13:5] sbz;
- logic[4:3] rgn;
- logic[2:2] imp;
- logic[1:1] s;
- logic[0:0] c;
-} cp15_ttbr;
-
-`endif
diff --git a/rtl/core/cp15/syscfg.sv b/rtl/core/cp15/syscfg.sv
deleted file mode 100644
index 5bd2530..0000000
--- a/rtl/core/cp15/syscfg.sv
+++ /dev/null
@@ -1,68 +0,0 @@
-`include "core/uarch.sv"
-`include "core/cp15/map.sv"
-
-module core_cp15_syscfg
-(
- input logic clk,
- rst_n,
-
- input logic load,
- transfer,
- input cp_opcode op2,
- input word write,
-
- output word read,
- output logic high_vectors,
- mmu_enable
-);
-
- logic dcache_enable, icache_enable;
-
- cp15_syscfg_ctrl ctrl /*verilator public*/, write_ctrl;
-
- assign write_ctrl = write;
-
- always_comb begin
- ctrl = {$bits(ctrl){1'b0}};
- ctrl.m = mmu_enable;
- ctrl.c = dcache_enable;
- ctrl.l = 1;
- ctrl.d = 1;
- ctrl.p = 1;
- ctrl.z = 1;
- ctrl.i = icache_enable;
- ctrl.v = high_vectors;
- ctrl.dt = 1;
- ctrl.it = 1;
-
- unique case(op2)
- `CP15_SYSCFG_CTRL:
- read = ctrl;
-
- `CP15_SYSCFG_ACCESS:
- read = 0;
-
- default:
- read = 0;
- endcase
- end
-
- always @(posedge clk or negedge rst_n)
- if(!rst_n) begin
- mmu_enable <= 0;
- high_vectors <= 0;
- dcache_enable <= 0;
- icache_enable <= 0;
- end else if(transfer && !load)
- unique case(op2)
- `CP15_SYSCFG_CTRL: begin
- mmu_enable <= write_ctrl.m;
- high_vectors <= write_ctrl.v;
- dcache_enable <= write_ctrl.c;
- icache_enable <= write_ctrl.i;
- end
-
- default: ;
- endcase
-
-endmodule
diff --git a/rtl/core/cp15/tlb.sv b/rtl/core/cp15/tlb.sv
deleted file mode 100644
index 5cbd19d..0000000
--- a/rtl/core/cp15/tlb.sv
+++ /dev/null
@@ -1,15 +0,0 @@
-`include "core/uarch.sv"
-
-module core_cp15_tlb
-(
- input logic clk,
- rst_n,
-
- input logic load,
- transfer,
- input word write
-);
-
- //TODO
-
-endmodule
diff --git a/rtl/core/cp15/tlb_lockdown.sv b/rtl/core/cp15/tlb_lockdown.sv
deleted file mode 100644
index 1972c33..0000000
--- a/rtl/core/cp15/tlb_lockdown.sv
+++ /dev/null
@@ -1,18 +0,0 @@
-`include "core/uarch.sv"
-
-module core_cp15_tlb_lockdown
-(
- input logic clk,
- rst_n,
-
- input logic load,
- transfer,
- input word write,
-
- output word read
-);
-
- //TODO, aunque al parecer Linux no usa esto
- assign read = 0;
-
-endmodule
diff --git a/rtl/core/cp15/ttbr.sv b/rtl/core/cp15/ttbr.sv
deleted file mode 100644
index b462955..0000000
--- a/rtl/core/cp15/ttbr.sv
+++ /dev/null
@@ -1,45 +0,0 @@
-`include "core/cp15/map.sv"
-`include "core/mmu/format.sv"
-`include "core/uarch.sv"
-
-module core_cp15_ttbr
-(
- input logic clk,
- rst_n,
-
- input logic load,
- transfer,
- input word write,
-
- output word read /*verilator public*/,
- output mmu_base mmu_ttbr
-);
-
- logic s, c;
- cp15_ttbr read_ttbr, write_ttbr;
- logic[1:0] rgn;
-
- assign read = read_ttbr;
- assign write_ttbr = write;
-
- assign read_ttbr.s = s;
- assign read_ttbr.c = c;
- assign read_ttbr.sbz = 9'd0;
- assign read_ttbr.rgn = rgn;
- assign read_ttbr.imp = 0;
- assign read_ttbr.base = mmu_ttbr;
-
- always @(posedge clk or negedge rst_n)
- if(!rst_n) begin
- s <= 0;
- c <= 0;
- rgn <= 0;
- mmu_ttbr <= 0;
- end else if(transfer && !load) begin
- s <= write_ttbr.s;
- c <= write_ttbr.c;
- rgn <= write_ttbr.rgn;
- mmu_ttbr <= write_ttbr.base;
- end
-
-endmodule
generated by cgit v1.2.3 (git 2.25.1) at 2026-04-17 15:52:23 +0000