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-rw-r--r--rtl/core/control/ldst/ldst.sv129
-rw-r--r--rtl/core/control/ldst/pop.sv56
-rw-r--r--rtl/core/control/ldst/sizes.sv46
3 files changed, 0 insertions, 231 deletions
diff --git a/rtl/core/control/ldst/ldst.sv b/rtl/core/control/ldst/ldst.sv
deleted file mode 100644
index aa5c957..0000000
--- a/rtl/core/control/ldst/ldst.sv
+++ /dev/null
@@ -1,129 +0,0 @@
-`include "core/uarch.sv"
-
-module core_control_ldst
-(
- input logic clk,
- rst_n,
-
- input insn_decode dec,
- input logic issue,
- mem_ready,
- mem_ex_fail,
- input word rd_value_b,
- q_alu,
- q_shifter,
-
- input ctrl_cycle cycle,
- next_cycle,
- input word alu_a,
- alu_b,
-
- output ptr mem_addr,
- output logic[3:0] mem_data_be,
- output word mem_data_wr,
- mem_offset,
- output logic mem_start,
- mem_write,
- mem_ex_lock,
- mem_user,
- pop_valid,
- ldst,
- ldst_next,
- ldst_reject,
- ldst_writeback,
- output logic[1:0] ldst_shift,
- output word ldst_read,
- strex_ok,
- output reg_num popped
-);
-
- word base;
- logic block_strex, increment, pre, sign_extend;
- reg_num popped_upper, popped_lower;
- reg_list mem_regs, next_regs_upper, next_regs_lower;
- ldst_size size;
-
- assign popped = increment ? popped_lower : popped_upper;
- assign ldst_next = !cycle.transfer || mem_ready;
- assign mem_data_wr = mem_ex_lock ? alu_b : q_shifter;
-
- assign strex_ok = {31'd0, mem_ex_fail || block_strex};
- assign ldst_reject = mem_ex_lock && mem_write && block_strex;
-
- core_control_ldst_pop pop
- (
- .regs(mem_regs),
- .valid(pop_valid),
- .next_upper(next_regs_upper),
- .next_lower(next_regs_lower),
- .pop_upper(popped_upper),
- .pop_lower(popped_lower)
- );
-
- core_control_ldst_sizes sizes
- (
- .addr(mem_addr),
- .read(ldst_read),
- .shift(ldst_shift),
- .fault(), //TODO: alignment check
- .byteenable(mem_data_be),
- .*
- );
-
- always_ff @(posedge clk or negedge rst_n)
- if (!rst_n) begin
- pre <= 0;
- ldst <= 0;
- size <= LDST_WORD;
- increment <= 0;
- block_strex <= 1;
- sign_extend <= 0;
- ldst_writeback <= 0;
-
- base <= {$bits(base){1'b0}};
- mem_regs <= {$bits(mem_regs){1'b0}};
- mem_user <= 0;
- mem_write <= 0;
- mem_start <= 0;
- mem_offset <= 0;
- mem_ex_lock <= 0;
- end else begin
- if (mem_start)
- mem_start <= 0;
-
- if (next_cycle.issue) begin
- if (issue) begin
- ldst <= dec.ctrl.ldst;
- mem_user <= dec.ldst.unprivileged;
- end
-
- pre <= dec.ldst.pre_indexed;
- size <= dec.ldst.size;
- increment <= dec.ldst.increment;
- sign_extend <= dec.ldst.sign_extend;
- ldst_writeback <= dec.ldst.writeback;
-
- mem_regs <= dec.ldst.regs;
- mem_write <= !dec.ldst.load;
- mem_ex_lock <= dec.ldst.exclusive;
- end else if (next_cycle.transfer) begin
- if (!cycle.transfer) begin
- ldst <= 0;
- mem_offset <= alu_b;
- end
-
- if (ldst_next) begin
- base <= pre ? q_alu : alu_a;
- mem_regs <= increment ? next_regs_lower : next_regs_upper;
- end
-
- mem_start <= (!cycle.transfer || (mem_ready && pop_valid)) && !ldst_reject;
-
- if (block_strex)
- block_strex <= !mem_ex_lock || mem_write;
- end else if (cycle.escalate) begin
- ldst <= 0;
- block_strex <= 1;
- end
- end
-endmodule
diff --git a/rtl/core/control/ldst/pop.sv b/rtl/core/control/ldst/pop.sv
deleted file mode 100644
index 64dc04d..0000000
--- a/rtl/core/control/ldst/pop.sv
+++ /dev/null
@@ -1,56 +0,0 @@
-`include "core/uarch.sv"
-
-module core_control_ldst_pop
-(
- input reg_list regs,
-
- output logic valid,
- output reg_list next_upper,
- next_lower,
- output reg_num pop_upper,
- pop_lower
-);
-
- assign valid = regs != 16'b0;
-
- always_comb begin
- unique casez(regs)
- 16'b???????????????1: begin pop_lower = 4'h0; next_lower = {regs[15:1], 1'b0}; end
- 16'b??????????????10: begin pop_lower = 4'h1; next_lower = {regs[15:2], 2'b0}; end
- 16'b?????????????100: begin pop_lower = 4'h2; next_lower = {regs[15:3], 3'b0}; end
- 16'b????????????1000: begin pop_lower = 4'h3; next_lower = {regs[15:4], 4'b0}; end
- 16'b???????????10000: begin pop_lower = 4'h4; next_lower = {regs[15:5], 5'b0}; end
- 16'b??????????100000: begin pop_lower = 4'h5; next_lower = {regs[15:6], 6'b0}; end
- 16'b?????????1000000: begin pop_lower = 4'h6; next_lower = {regs[15:7], 7'b0}; end
- 16'b????????10000000: begin pop_lower = 4'h7; next_lower = {regs[15:8], 8'b0}; end
- 16'b???????100000000: begin pop_lower = 4'h8; next_lower = {regs[15:9], 9'b0}; end
- 16'b??????1000000000: begin pop_lower = 4'h9; next_lower = {regs[15:10], 10'b0}; end
- 16'b?????10000000000: begin pop_lower = 4'ha; next_lower = {regs[15:11], 11'b0}; end
- 16'b????100000000000: begin pop_lower = 4'hb; next_lower = {regs[15:12], 12'b0}; end
- 16'b???1000000000000: begin pop_lower = 4'hc; next_lower = {regs[15:13], 13'b0}; end
- 16'b??10000000000000: begin pop_lower = 4'hd; next_lower = {regs[15:14], 14'b0}; end
- 16'b?100000000000000: begin pop_lower = 4'he; next_lower = {regs[15], 15'b0}; end
- default: begin pop_lower = 4'hf; next_lower = 16'b0; end
- endcase
-
- unique casez(regs)
- 16'b1???????????????: begin pop_upper = 4'hf; next_upper = { 1'b0, regs[14:0]}; end
- 16'b01??????????????: begin pop_upper = 4'he; next_upper = { 2'b0, regs[13:0]}; end
- 16'b001?????????????: begin pop_upper = 4'hd; next_upper = { 3'b0, regs[12:0]}; end
- 16'b0001????????????: begin pop_upper = 4'hc; next_upper = { 4'b0, regs[11:0]}; end
- 16'b00001???????????: begin pop_upper = 4'hb; next_upper = { 5'b0, regs[10:0]}; end
- 16'b000001??????????: begin pop_upper = 4'ha; next_upper = { 6'b0, regs[9:0]}; end
- 16'b0000001?????????: begin pop_upper = 4'h9; next_upper = { 7'b0, regs[8:0]}; end
- 16'b00000001????????: begin pop_upper = 4'h8; next_upper = { 8'b0, regs[7:0]}; end
- 16'b000000001???????: begin pop_upper = 4'h7; next_upper = { 9'b0, regs[6:0]}; end
- 16'b0000000001??????: begin pop_upper = 4'h6; next_upper = {10'b0, regs[5:0]}; end
- 16'b00000000001?????: begin pop_upper = 4'h5; next_upper = {11'b0, regs[4:0]}; end
- 16'b000000000001????: begin pop_upper = 4'h4; next_upper = {12'b0, regs[3:0]}; end
- 16'b0000000000001???: begin pop_upper = 4'h3; next_upper = {13'b0, regs[2:0]}; end
- 16'b00000000000001??: begin pop_upper = 4'h2; next_upper = {14'b0, regs[1:0]}; end
- 16'b000000000000001?: begin pop_upper = 4'h1; next_upper = {15'b0, regs[0]}; end
- default: begin pop_upper = 4'h0; next_upper = 16'b0; end
- endcase
- end
-
-endmodule
diff --git a/rtl/core/control/ldst/sizes.sv b/rtl/core/control/ldst/sizes.sv
deleted file mode 100644
index dff4662..0000000
--- a/rtl/core/control/ldst/sizes.sv
+++ /dev/null
@@ -1,46 +0,0 @@
-`include "core/uarch.sv"
-
-module core_control_ldst_sizes
-(
- input word base,
- q_shifter,
- input ldst_size size,
- input logic sign_extend,
-
- output ptr addr,
- output word read,
- output logic[1:0] shift,
- output logic[3:0] byteenable,
- output logic fault
-);
-
- assign {addr, shift} = base;
-
- always_comb
- unique case(size)
- LDST_BYTE: begin
- read = {{24{q_shifter[7] && sign_extend}}, q_shifter[7:0]};
- fault = 0;
-
- unique case(shift)
- 2'b00: byteenable = 4'b0001;
- 2'b01: byteenable = 4'b0010;
- 2'b10: byteenable = 4'b0100;
- 2'b11: byteenable = 4'b1000;
- endcase
- end
-
- LDST_HALF: begin
- read = {{16{q_shifter[15] && sign_extend}}, q_shifter[15:0]};
- fault = shift[0];
- byteenable = shift[1] ? 4'b1100 : 4'b0011;
- end
-
- LDST_WORD: begin
- read = q_shifter;
- fault = shift[1] || shift[0];
- byteenable = 4'b1111;
- end
- endcase
-
-endmodule
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