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-rw-r--r--rtl/core/control/issue.sv4
1 files changed, 2 insertions, 2 deletions
diff --git a/rtl/core/control/issue.sv b/rtl/core/control/issue.sv
index b2ee6e5..c1c932e 100644
--- a/rtl/core/control/issue.sv
+++ b/rtl/core/control/issue.sv
@@ -23,7 +23,7 @@ module core_control_issue
next_pc_visible
);
- assign issue = next_cycle == ISSUE && dec.ctrl.execute && !next_bubble && !halt;
+ assign issue = next_cycle.issue && dec.ctrl.execute && !next_bubble && !halt;
assign next_pc_visible = insn_pc + 2;
always_ff @(posedge clk or negedge rst_n)
@@ -31,7 +31,7 @@ module core_control_issue
pc <= 0;
undefined <= 0;
pc_visible <= 2;
- end else if(next_cycle == ISSUE) begin
+ end else if(next_cycle.issue) begin
undefined <= dec.ctrl.undefined;
`ifdef VERILATOR